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Contributor
Contributor
4,950 Views
Registered: ‎04-22-2014

spartan 6 synthesis

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Hi,

 

I synthesizing the SATA with spartan phy.

 

PACKAGE is XCSLX75T FGG484 -3

 

In the disign , cloks with differential ports are exsist.

 

When synthesising the desing with XILINX 13.2 ISE getting following error.

 

Section 1 - Errors
------------------
ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
   single IOB component because the site type selected is not compatible.

   Further explanation:
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. In this case an IO component of type
   IOB was chosen because the IO contains symbols and/or properties consistent
   with input, output, or bi-directional usage and contains no other symbols or
   properties that require a more specific IO component type. Please double
   check that the types of logic elements and all of their relevant properties
   and configuration options are compatible with the physical site type of the
   constraint.

   Summary:
   Symbols involved:
       PAD symbol "pad_TS_sata_pll_ref_clk_n" (Pad Signal =
   pad_TS_sata_pll_ref_clk_n)
       SlaveBuffer symbol "U_PHY_VH_VD/U_serdes_clk/

SLAVEBUF.DIFFIN" (Output Signal
   = U_PHY_VH_VD/U_serdes_clk/SLAVEBUF.DIFFIN)
   Component type involved: IOB
   Site Location involved: B10
   Site Type involved: IPAD

ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
   single IOB component because the site type selected is not compatible.

   Further explanation:
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. In this case an IO component of type
   IOB was chosen because the IO contains symbols and/or properties consistent
   with input, output, or bi-directional usage and contains no other symbols or
   properties that require a more specific IO component type. Please double
   check that the types of logic elements and all of their relevant properties
   and configuration options are compatible with the physical site type of the
   constraint.

   Summary:
   Symbols involved:
       PAD symbol "pad_TS_sata_pll_ref_clk_p" (Pad Signal =
   pad_TS_sata_pll_ref_clk_p)
       DIFFAMP symbol "U_PHY_VH_VD/U_serdes_clk/IBUFDS" (Output Signal =
   U_PHY_VH_VD/clk_150M)
   Component type involved: IOB
   Site Location involved: A10
   Site Type involved: IPAD
 
 
So can any one help me to resolve this issue.
 
Thanking you,
 
regards
P Dasarath
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1 Solution

Accepted Solutions
Moderator
Moderator
8,431 Views
Registered: ‎02-16-2010

Re: spartan 6 synthesis

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Whether the clock pins shown in error are GT input refclks?

From error message it shows that these clocks are assigned to normal IOBs. Please assign the clock to the GT refclk input pins.
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1 Reply
Moderator
Moderator
8,432 Views
Registered: ‎02-16-2010

Re: spartan 6 synthesis

Jump to solution
Whether the clock pins shown in error are GT input refclks?

From error message it shows that these clocks are assigned to normal IOBs. Please assign the clock to the GT refclk input pins.
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos