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Observer
Observer
3,946 Views
Registered: ‎09-11-2008

spartan3 slave serial problem

dear all,

m trying to configure the fpga(spartan3- xc3s400pq208) through the process described in xapp502. m using slave serial mode. i have used 8051 mc to do the configuration.
following is the assemble program that i hae written for programming:



$ include (reg51.inc)

DIN EQU P1.0 ; interface with fpga
INIT BIT P1.1 ; interface with fpga for checking the init status

DONE BIT P1.2 ;interface with fpga
PROG EQU P1.3 ; for reseting fpga
CLK EQU P1.4 ;for providing clk
INITCHECK EQU P1.5 ; for reading the init status from fpga
DCHECK EQU P1.6 ; for checking the done pin status from fpga


ORG 0000H ; main
CLR INITCHECK ;
CLR DCHECK ;
SETB INIT ;
HERE: JNB INIT ,HERE ;remain here till the init goes high. i m manually giving the pulse at progb pin after applling power. so no software pulse on ;progb pin

SETB INITCHECK

MOV DPTR, #2000H

NEXTLOC : CLR A
MOVX A,@DPTR
MOV R2 , A
ACALL SERIAL ; serialize the data
MOV A , DPL
MOV R5 , A
MOV A , DPH
MOV R6 ,A
INC DPTR
CJNE R5 , #5FH, NEXTLOC ; last adderess reached?, then stop else continue

CJNE R6 , #77H, NEXTLOC
SETB DONE
JNB DONE, CCLK
SETB DCHECK


CCLK : ACALL CLKDONE
STOP : SJMP STOP



SERIAL : MOV R4,#08H
MOV A , #01H
UP: MOV R3 , A
ANL A, R2
JZ ZEROOUT
SETB DIN
ACALL CLKCALL
SJMP NEXT
ZEROOUT : CLR DIN
ACALL CLKCALL
NEXT : MOV A, R3
RL A
DJNZ R4, UP
RET


CLKCALL : CLR CLK
SETB CLK
CLR CLK
RET


CLKDONE : CLR CLK
SETB CLK
CLR CLK
SETB DONE
JNB DONE , CLKDONE
SETB DCHECK
RET

END

















can u pls help me with this code and the interface.



things i have analysed:


done goes high after 10-15 sec. but the configuration is not sucessful.

i have directly loaded the *.bit file in the EEPROM used for storing the configuration data.

i have also tried with hex file for configuration.

thanks in advance!
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2 Replies
Xilinx Employee
Xilinx Employee
3,903 Views
Registered: ‎08-07-2007

after done goes high, do you still send additional pulses to cclk?

you should send some more cycles of cclk after done goes high.

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Observer
Observer
3,888 Views
Registered: ‎09-11-2008

how many more clocks???? pls specify...
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