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Explorer
Explorer
1,690 Views
Registered: ‎03-08-2018

spartan6lx16 ft256-C2 pll clocking generation issue

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Dear All,

 

I'm trying to make a 750Mhz clock from 50Mhz internal clock by using clocking wizard in coregen on spartan6lx16 ft256-C2.

 

After generation 750Mhz PLL clock, I've got the below warning messages ( don't meet timing )

 

WARNING:Pack:1653 - At least one timing constraint is impossible to meet because component delays alone exceed the constraint. A timing
   constraint summary below shows the failing constraints (preceded with an Asterisk (*)). Please use the Timing Analyzer (GUI) or TRCE
   (command line) with the Mapped NCD and PCF files to identify which constraints and paths are failing because of the component delays
   alone. If the failing path(s) is mapped to Xilinx components as expected, consider relaxing the constraint. If it is not mapped to
   components as expected, re-evaluate your HDL and how synthesis is optimizing the path. To allow the tools to bypass this error, set the
   environment variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1.
WARNING:Par:450 - At least one timing constraint is impossible to meet because component switching limit violations have been detected for a
   constrained component. A timing constraint summary below shows the failing constraints (preceded with an Asterisk (*)). Please use the
   Timing Analyzer (GUI) or TRCE (command line) with the Mapped NCD and PCF files to evaluate the component switching limit violations in
   more detail. Evaluate the datasheet for alternative configurations for the component that could allow the frequencies requested in the
   constraint. Otherwise, the timing constraint covering this component might need to be modified to satisfy the component switching limits
   specified in the datasheet.
WARNING:Par:468 - Your design did not meet timing.  The following are some suggestions to assist you to meet timing in
   your design.

What am I supposed to do to resolve this problem?

 

I've implemented as the below

 

module test(
...
);


  clocking clocking_block(
    .CLK_IN(CLK),
    .CLK_OUT(pclk));

PLL_BASE
  #(.BANDWIDTH              ("OPTIMIZED"),
    .CLK_FEEDBACK           ("CLKFBOUT"),
    .COMPENSATION           ("SYSTEM_SYNCHRONOUS"),
    .DIVCLK_DIVIDE          (1),
    .CLKFBOUT_MULT          (5),
    .CLKFBOUT_PHASE         (0.000),
    .CLKOUT0_DIVIDE         (5),
    .CLKOUT0_PHASE          (0.000),
    .CLKOUT0_DUTY_CYCLE     (0.500),
    .CLKOUT1_DIVIDE         (1),
    .CLKOUT1_PHASE          (0.000),
    .CLKOUT1_DUTY_CYCLE     (0.500),
    .CLKIN_PERIOD           (6.666),
    .REF_JITTER             (0.010))
  pll_base_inst
    // Output clocks
   (.CLKFBOUT              (clkfbout),
    .CLKOUT0               (pllclk0), //150Mhz
    .CLKOUT1               (pllclk2), //750Mhz
    .CLKOUT2               (clkout2_unused),
    .CLKOUT3               (clkout3_unused),
    .CLKOUT4               (clkout4_unused),
    .CLKOUT5               (clkout5_unused),
    // Status and control signals
    .LOCKED                (plllckd),
    .RST                   (pll_reset),
     // Input clock control
    .CLKFBIN               (clkfbin),
    .CLKIN                 (pclk)
	 );
	  
	   //-----------------------------------
  BUFG clkf_buf
   (.O (clkfbin),
    .I (clkfbout));

  BUFG clkout1_buf
   (.O   (pclkx2),
    .I   (pllclk2));
	
 BUFPLL #(.DIVIDE(5)) ioclk_buf (.PLLIN(pllclk0), .GCLK(pclkx2), .LOCKED(plllckd),
           .IOCLK(pclkx10), .SERDESSTROBE(serdesstrobe), .LOCK(bufpll_lock));
		  
...

endmodule


(* CORE_GENERATION_INFO = "clocking,clk_wiz_v3_6,{component_name=clocking,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)

module clocking
 (// Clock in ports
  input         CLK_IN,
  // Clock out ports
  output        CLK_OUT
 );

  // Input buffering
  //------------------------------------
  IBUFG clkin1_buf
   (.O (clkin1),
    .I (CLK_IN));


  // Clocking primitive
  //------------------------------------

  // Instantiation of the DCM primitive
  //    * Unused inputs are tied off
  //    * Unused outputs are labeled unused
  wire        psdone_unused;
  wire        locked_int;
  wire [7:0]  status_int;
  wire clkfb;
  wire clk0;
  wire clkfx;

  DCM_SP
  #(.CLKDV_DIVIDE          (2.000),
  
    .CLKFX_DIVIDE          (1),//(1),     //Original (2), //100->150
    .CLKFX_MULTIPLY        (3),
	 
    .CLKIN_DIVIDE_BY_2     ("FALSE"),
    .CLKIN_PERIOD          (20.0),//(20.0),  //Original (10.0),//100->150
    .CLKOUT_PHASE_SHIFT    ("NONE"),
    .CLK_FEEDBACK          ("1X"),
    .DESKEW_ADJUST         ("SYSTEM_SYNCHRONOUS"),
    .PHASE_SHIFT           (0),
    .STARTUP_WAIT          ("FALSE"))
  dcm_sp_inst
    // Input clock
   (.CLKIN                 (clkin1),
    .CLKFB                 (clkfb),
    // Output clocks
    .CLK0                  (clk0),
    .CLK90                 (),
    .CLK180                (),
    .CLK270                (),
    .CLK2X                 (),
    .CLK2X180              (),
    .CLKFX                 (clkfx),
    .CLKFX180              (),
    .CLKDV                 (),
    // Ports for dynamic phase shift
    .PSCLK                 (1'b0),
    .PSEN                  (1'b0),
    .PSINCDEC              (1'b0),
    .PSDONE                (),
    // Other control and status signals
    .LOCKED                (locked_int),
    .STATUS                (status_int),
    .RST                   (1'b0),
    // Unused pin- tie low
    .DSSEN                 (1'b0));


  // Output buffering
  //-----------------------------------
  BUFG clkf_buf
   (.O (clkfb),
    .I (clk0));

  BUFG clkout1_buf
   (.O   (CLK_OUT),
    .I   (clkfx));




endmodule

..

 

 

 

 

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1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
1,585 Views
Registered: ‎06-30-2010

Re: spartan6lx16 ft256-C2 pll clocking generation issue

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@love119 how are you getting on, as the other contributors here have explained the Fmax of the FPGA fabric is 400Mhz (page 56 of the data sheet) however that will reduce based on how you design is implemented and the skew on the clock net. As bruce mentioned you should have a timing report showing the nets that have failed timing or you can apply this environment variable to allow placement to complete with errors environment variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1. this will allow you to cross probe the design in FPGA editor to see what nets are failing and where they are placed.
-------------------------------------------------------------------------
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10 Replies
Explorer
Explorer
1,669 Views
Registered: ‎05-08-2018

Re: spartan6lx16 ft256-C2 pll clocking generation issue

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Unlikely this will ever work,

 

As you are out of the device operating specifications.

 

Table 48 and on in data sheet ... beyond Fmax

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Scholar jmcclusk
Scholar
1,668 Views
Registered: ‎02-24-2014

Re: spartan6lx16 ft256-C2 pll clocking generation issue

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750 MHz is WAY too fast for a Spartan6 device..     the absolute maximum for Spartan6 is about 400 MHz.    Reduce your clock speed, and the errors will go away.

Don't forget to close a thread when possible by accepting a post as a solution.
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Explorer
Explorer
1,654 Views
Registered: ‎03-08-2018

Re: spartan6lx16 ft256-C2 pll clocking generation issue

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@alesea Would you let me know what document should I have to see?

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Explorer
Explorer
1,645 Views
Registered: ‎03-08-2018

Re: spartan6lx16 ft256-C2 pll clocking generation issue

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@jmcclusk @alesea

Thanks for your opinions. but 

When I use input clock to 100Mhz, then there is no timing error, 

I've updated files, you can see that at ori.7z

 

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Xilinx Employee
Xilinx Employee
1,639 Views
Registered: ‎11-03-2016

Re: spartan6lx16 ft256-C2 pll clocking generation issue

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That's DS162, Spartan6 's datasheet. While the PLL can reach such frequency, fabric can't. The 400MHz logic jmcclusk is the best (theoritical and garanteed) you can get. This comes from the limit imposed by the BUFGMUXs which drives the rest of the clock tree. Even 300MHz is not so trivial to hit with well pipelined logic on a -3, let alone a -2.

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Highlighted
Explorer
Explorer
1,636 Views
Registered: ‎05-08-2018

Re: spartan6lx16 ft256-C2 pll clocking generation issue

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Explorer
Explorer
1,632 Views
Registered: ‎05-08-2018

Re: spartan6lx16 ft256-C2 pll clocking generation issue

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l,

 

And, my car will go 6 miles per hour.  Does that tell you how much faster it can go?

 

No, it does not.

 

A design goes only as fast as it was constrained successfully to run at (meeting all recommended operating conditions and device data sheet specifications).

 

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Explorer
Explorer
1,589 Views
Registered: ‎03-08-2018

Re: spartan6lx16 ft256-C2 pll clocking generation issue

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@yannickl @alesea @jmcclusk

 

Dear @yannickl

 

As your recommend, I did decrease the timing to 250Mhz from 400Mhz.

But I have still the timing error.

WARNING:Pack:1653 - At least one timing constraint is impossible to meet because component delays alone exceed the constraint. A timing
   constraint summary below shows the failing constraints (preceded with an Asterisk (*)). Please use the Timing Analyzer (GUI) or TRCE
   (command line) with the Mapped NCD and PCF files to identify which constraints and paths are failing because of the component delays
   alone. If the failing path(s) is mapped to Xilinx components as expected, consider relaxing the constraint. If it is not mapped to
   components as expected, re-evaluate your HDL and how synthesis is optimizing the path. To allow the tools to bypass this error, set the
   environment variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1.
WARNING:Par:468 - Your design did not meet timing.  The following are some suggestions to assist you to meet timing in your design.

Can't I use PLL to make 250Mhz clock ?

I've updated to project. Could you please help me a bit?

 

 

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1,573 Views
Registered: ‎06-21-2017

Re: spartan6lx16 ft256-C2 pll clocking generation issue

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There should be a report that tells you which net(s) didn't meet timing constraints.  Are these nets in your clock generation code or somewhere else?  Even 250MHz is non-trivial in a Spartan 6 if you have multiple levels of logic between registers. 

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Xilinx Employee
Xilinx Employee
1,586 Views
Registered: ‎06-30-2010

Re: spartan6lx16 ft256-C2 pll clocking generation issue

Jump to solution
@love119 how are you getting on, as the other contributors here have explained the Fmax of the FPGA fabric is 400Mhz (page 56 of the data sheet) however that will reduce based on how you design is implemented and the skew on the clock net. As bruce mentioned you should have a timing report showing the nets that have failed timing or you can apply this environment variable to allow placement to complete with errors environment variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1. this will allow you to cross probe the design in FPGA editor to see what nets are failing and where they are placed.
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos