10-26-2010 04:17 AM
Please helpme with this programm.
What i need is below:
Input to the state machine is an 8 bit value named OPC (OpCode), representing one machine instruction (corresponds to one assembler instruction) for a simple microcontroller.
Outputs from the state machine: all necessary control signals needed to control the data path developed in assignments D flip-flop, Counter and shift register( which connetcting all together).
By connecting the data path and the state machine, we can create a very simple microcontroller – let’s just call it XSMC (XtremeSimpleMicroController).
This circuit is the basis of the following questions.
The sequence for the state machine is: instruction fetch -> data fetch -> instruction execute, where the instructions are placed in a constant memory (8 bit wide) – the program memory. Constant data can be placed in the program memory as part of the instruction (second byte) or in a ram memory. Not all instructions include data fetch.
Fetching instructions from the program memory is normally done by a circuit called the instruction fetch unit (IFU). The IFU will keep track of the program counter – a register that always points at the location (address) of the next instruction.
Question 3.1: The assembler instructions: LOAD_A, input; LOAD_B, input; LOAD_C, input; LOAD_D, input are defined by the corresponding OPC values: 0001000; 00010001; 00010010; 00010011, where input is the 8 bit value on the input of the multiplexer in the data path (the C-bus) – consider this as an input port.
Create a state machine that continuously will read the OPC from a program memory and perform the corresponding above mentioned operations in the XSMC. Draw the expected timing diagram for relevant signals, including the global clock and reset signals, before doing any VHDL design.
10-26-2010 04:48 AM
at first: Know that you are about to design a hardware, not writing a programm!
To create the desired FSM your first step is to identify the necessary inputs and outputs.
Second, you draw a state diagram that specifies which sequential steps have to be performed for the assignment.
Some timing scetches might also be useful, for better understanding the design goal.
Third, write the code and simulate it. You find examples for good FSMs in the forums.
Have a nice synthesis
10-28-2010 06:56 AM
besides topos like "Refister_C" and "schemetic" you have a multiple driver problem.
It is not allowed to wire outputs of severl modules directly together. (Unless you could tristate the outputs, which you can't in modern FPGAs for internal signals)
I will take another look tomorrom..
Have a nice synthesis
10-29-2010 12:44 AM
it's kind of confusing.
In your first post you ask about how to design a FSM,
now you are creating a strange IFU-replacement.
Its obvious that you can't design a FSM without having a proper datapath.
So let's take a look at what you have done so far:
Your design schematic_shift_reg consists of 4 registers a weird mux and a strange ALU (schemetic).
Except for the registers nothing is clocked.
There's just one Data Input (C) and one Data Output (Pout) (plus the carrys from the alu)
One strange part is the NEW_MUX.
It ony works on two (inverted) datawords of C.
Since there is no else branch, it creates some latches (Latches = bad thing)
You could overcome this by making it a registered mux (with clk input).
Also you mix numeric_std with std_logic_arit/unsigned. Also a bad thing.
Since you are a beginner, only use numeric_std in the future.
Why does the output selection of NEW_MUX depend on the Value of C? Makes no sense to me.
The registers are OK so far, since they are designed to tristate their outputs. As said before, there are no real tristate buffers available in the FPGA fabric, so these will be converted into a (large) mux. You can see it when you take a look at the technology schematic.
Your ALU (schemetic) also is unregistered.
The adder (assign1) looks like taken from a textbook chapter about loops.
the whole stuff could be written in a few lines of code:
result <= '0'&a +' 0'&b + cin;
sum <= result(sum'high downto 0);
cout <= result(result'high);
(This is just a meta example, not syntax checked !!!)
You may use this as an suggestion for more effective coding.
Depending on the libraries you use (numeric_std recommended) the signal types and type conversions have to be chosen. I leave this to you as a little brain teaser.
Another thing I found:
In the sensitivity list of your counter you wrote (clk, updown) which is wrong. Should be (reset, clk).
Also you may consider to use rising_edge(clk) instead of the clk'event thing.
So, once you have reworked this stuff, you have a lot of enables and select lines.
These have to be driven from the FSM you are about to design. Still the FSM needs input.
Some part of an OPCODE, as far as I understand. But you have to define that more precisely, since the block diagram in your PDF is not really helpful for that. (e.g. ther's a vertical Block called PC and in your IFU replacement is another block with the same name. So, which one is what?
Maybe you should take a look at some other microprocessor design first. A simple one would be the PicoBlaze.
Take a look at its structure and how it works and comparte this with your design.
Use the weekend to muse about it and work out something.
Have a nice synthesis
10-29-2010 02:46 AM
I appriciated what you are writing but I am also confused. I will tell you the history
I am studying University of Southern Denamrk in Mechatronics. I have never had programed in VHDL before. This semester we have a class in VHDL and we have Assigment in case to improve them we can pass this course without exam.
In the assignment 1 we made multiplexer and ALU....... which approved from the teacher
In the assignment 2 we made D-F-F, counter and shift register...... which also approved
In the assignment 3 we have to make this complex State machine which I have no idea how to do it.
As you in the attachments this 3 assignments
10-29-2010 06:17 AM
if students just always would add the true assignments to their requests. It would help a lot.
On thing in advance: Coding single functional blocks like you did in Assignment 1 and 2 is quite a simple task.
Designing a system requires some additional skills, that you can not train that way. That's why you (and many other students) run into trouble at some point.
You mastered the assignments 1 and 2 quite well. Your instructor probably missed the litle error in the counter.
Only thing that went wrong is NEW_MUX. The switching mustn't depend on the input C just SELEC.
And then you can say
if selec = '1' then
-- mux path 1
-- mux path 2
to prevent latches. (Important!)
From Assignment1 I saw that the target device was a Spartan2. This FPGA-Family had real Tristate buffers in their fabric. But unfortunately it's no longer supported till ISE11.1. So you have to live with the multiplexers. Maybe your instructor should rewrite the assignments, unless the target hardware is still a Spartan2 devioce. In that case your implementation has to be made with ISE10.x again.
Now to assignment 3.
To be able to pass this assignment, it's of utter importance that you have understood the last part of assignment 2. The processors datapath. That is what you created with the Registers and your ALU.
You also have made a counter, that can be your "IFU". It's already (almost) done.
(If your processor had to perform branches you would have needed a loadable counter. )
But it needs either a Clock Enable, or count only when either up or down is asserted. This can't be acheived with a single up/down input. Check it.
So, what you need first is some ROM, where your program is stored.
In the Assignment only the LOAD instruction is defined. Do you have specifications for other opcodes?
You have a ALU, so you need at least opcodes like ADD, AND,OR and NOT.
How about addressing modes. Add constants? Or just register contents?
Is there RAM involved (see assignment) or some ports. Where do the results go?
Well, probably it's not meant to become so complex. :-)
Again. Take a look at the PicoBlaze, you can learn a lot from it for your assignment.
Assignment 3 gives you a lot of information (but maybe not all) that you need to design the FSM.
So you have some degree of freedom to be creative.
Still you need to make a proper design of the FSM.
The input is known, It's the content of the ROM (at certain times).
The output signals need to be collected and listed up to have a overview.
The basic sequence is described in the assignment. I see no restriction that these steps must be executed in a single clock cycle. May be useful. The result may not be optimal but save and easy to understand.
The part about the IFU seems to be only informational ("...is normally..." means "You do it different"). In your case a counter with CE is sufficient, where the counting register is equal to your program counter.
One final question:
Have you been talking about FSM design in your digital design lectures at all? (Bubble charts, State Coding etc.)
If not, you need to learn about it. FSMs are the point where true digital (systems) design begins.
The combinatorical and sequential stuff is just preparing the path for that topic.
Have a nice Synthesis
10-29-2010 12:25 PM
wow You are great person you game me a good idea.
Extually counter and Mux is the IFU.
I just made diagram and I got understood everything goes fine.
and as you said I need ROM 8bits.
The only thing is left i think is to make ROM 8bits and I dont know how to do it
Please take a look what I made today and say me your idea
Thank you alot that you are wasting your time for me, it is so kind of you
11-01-2010 01:53 AM
from the provided pictures, I see you are actually working hard on the design.
Some more hints:
Making a rom isn't very complicated. There are examples in the ISE Language Templates. Also look how it's done for the picoblaze.
There's a flaw with your IFU/Program counter.
What good is the mux behind the counter and the feedback path to the counters input?
First: You don't need a mux at that place. Just make your counter loadable.
Second: since the mux isn't registered it would cause timing problems. You probably want to implement jumps with it. But once the address is taken away from it's input the Rom Adress changes back to the counters value.
So, rework is needed here.
Your assembler command list:
You missed to add the second bytes where necessary. (e.g. Load) Especially for your Jump instruction you should make clear, wether you have only 16 possible addresses or if the address is to be expanded by a LSB-byte
A reset comand makes no real sense. Reset is a hardware thing, and shouldn't be done with a software command.
With IDLE you probably want to implement a NOP (No OPeration Command). This isn't necessary. You yet haven't defined a register swap command (e.g. LOAD Rdest, Rsource) with identical parameters it also does effectively nothing.
Another option, to ease the FSM design, would be to declare all undefined opcodes as IDLE/NOP. Thus you prevent that your CPU "runs wild" when reading nonsense from the ROM.
Also, in order to clean up your systems scetch, take a look at Fig. 7 of this article:
There you see the basic structure of an FSM.
In your sketch the big "LOGIC" rectangle probably stands for the FSM's output logic block.
Replace this and the little block in front of it by a large rectangle called FSM.
This makes your sketch more readable.
So in the end you have these blocks:
ROM, FSM, ALU, IFU/PC
Keep on making progress.
Have a nice synthesis
11-01-2010 08:03 AM
Thank you for your answer
So far I made the state machine which is include also the IFU (state machine,logic,counter and Mux is in one)
I made also the ROM 8 bits but I steel need to add something
I have state machine, Rom and assignment 2 and after that i have to make a schematic and connect them together
The problem is that in state machine when I am doing test bench there is an problem as you will see
The loada starting with 1 but in the VHDL code i said that in the begining the loada is 0. Logically the loada must be 1 after 10ns. why is that?
my second question is that do think i need something else for the ROM?
11-03-2010 02:11 AM
you should put the state signal in your waveform too.
Your HDL code looks good, at the first glimpse, but has one big flaw.
A FSM needs to look ath the current state and the inputs to decide what to do next.
But in your next_state_decode process, you are just looking at the inputs, namely OPC.
In the assignment it's already mentioned that the FSM needs states (or phases, if more than one state is used) like fetch, decode and execute.
You will understand why, when you try to do something more than recognizing the Opcodes.
Think about this:
Where is the data stored that the load instruction shall place in the register?
How, and when, will you acess it?
When will you trigger operations of your ALU?
The rom seems OK. Here's one hint, how you can made the contents more readable, for easing the maintainance:
constant LOADA : std_logic_vector (7 downto 0) := "00010000";
constant LOADB : std_logic_vector (7 downto 0) := "00010001";
constant LOADC : std_logic_vector (7 downto 0) := "00010010";
constant LOADD : std_logic_vector (7 downto 0) := "00010011";
type rom_type is array (7 downto 0) of std_logic_vector (7 downto 0);
signal ROM : rom_type:= (LOADA,LOADB,LOADC,LOADD, "00010100","00010101","00010110","00010111");
So you can easily see, where you have an instruction, and where the data is.
Have a nice synthesis
11-09-2010 07:06 AM
I have made some changes
Now the state machine and the memory is working
I also made the final schematic but when I am doing test bench in simulink I have an stupid error
ERROR:HDLCompiler:806 - "C:/Users/chousi/assign3/schematictest2.vhd" Line 13: Syntax error near "<".
ERROR:HDLCompiler:806 - "C:/Users/chousi/assign3/schematictest2.vhd" Line 22: Syntax error near "<".
ERROR:HDLCompiler:806 - "C:/Users/chousi/assign3/schematictest2.vhd" Line 28: Syntax error near "<".
ERROR:ProjectMgmt:496 - 3 error(s) found while parsing design hierarchy.
Please take a look on it
11-09-2010 11:52 PM
Simulink? Don't you mean Modelsim or ISIM?
Anyway, have you ever taken a look at the file schematictest2.vhd ?
It's just an empty testbench template. This can't work.
Chevron-brackets "<...>" indicate placeholders that must be replaced with useful data,
therefore it's not valid VHDL and you get a syntax error.
Memorytest and mach_testbench are just fine.
Maybe something went wrong on automatic creation of the testbench.
Have a nice simulation
11-11-2010 10:27 AM
Thank you for the information
I have completed the assignment.
For the final assigment I have been given the choice of either editing the previous assigment and adding more features to it or make a completely new VHDL project.
Please suggest to me the opption I should go for. If you have some examples please send them to me.
For example like trafic signals, opening or closing the bridge for letting the boats to pass.