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saurabh_daimler
Observer
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Registered: ‎11-02-2011

xapp495 - 2x2 DVI Matrix

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Hi!  I was trying to run the two reference designs provided in xapp 495 on the Atlys board. The video timing controller runs fine. For the 2x2 DVI Matrix, I gave two inputs to connectors J1 and J3 by connecting them to display emulators (800x480) which are in turm connected to two different PCs. As a result, I expect to see the desktop wallpapaer of the two PCs on the two output display monitors. I am able to see the output of the source connected to connector J3 but not of the source connected to J1. I swapped the two input sources and found that the input source now connected to J3 gives the ouput but problem persists with the source connected to J1. This means my cables and two input sources are correct. I have tried all configuration of SW0, SW1. Both monitors display the ouput of the source connected to J3 when SW1 SW0 are 11 but nothing when SW1 SW0 are 00. I have tried this on 2 Atlys boards. What I also see is the LED above SW1 is never lit up ( though this might be totally unrelated). Can you tell me where am I going wrong?

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saurabh_daimler
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Registered: ‎11-02-2011

@joelby - Solved it ! :) :)

 

Problem was JP5 for connector J1.  JP5 is connected to ground on one end and not(OE) at the other. If I leave JP5 open, not(OE) gets the input 1 from VCCV3 resulting in no display for input source connected to J1. Therefore, JP5 should never be open. See the atlys schematic page 2 for more info.

 

Since I am using a display emulator, SCL and SDA info is given by the emulator also. But in general, JP2,6,7 should not be open in order to pass the SCL, SDA to the output. Now all get all the possible outputs on 2 displays.

 

SW1    SW0       Display1           Display2

0           0             source_J1        source_J1

0           1             source_J1        source_J3

1           0             source_J3        source_J1

1           1             source_J3        source_J3

 

where source_J1 = input source connected to connector J1, source_J3 = input source connected to connector J3, OE = output enable

 

Thanks a lot for your help !!

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saurabh_daimler
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Registered: ‎11-02-2011

I don't want to believe that there is something worng with the code. The input clock coming from the display emulators is 33.3 Mhz.

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joelby
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Registered: ‎10-05-2010

In the default configuration, the Atlys doesn't pass through HDMI EDID information, so displays/video sources that require it seem to fail. There's some information on this in another thread.

 

The Atlys has some jumpers that connect these through, though they aren't switched by the XAPP495 design. If your input and output devices are identical, there's ought to be no harm in passing them through. Have a look at the schematic diagram to see which jumpers these are and what they do (I just had a look at my board and it's JP6/JP7).

 

Please note that the jumper solution is still speculation on my part as I don't have enough HDMI sources to test this with.

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saurabh_daimler
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Registered: ‎11-02-2011

Thanks. I saw the manual(page 13, see attached) and for the connector J1, it seems that jumper JP2 needs to be connected. I can not find JP2 physically like JP6/JP7 on the board. Can you tell me how to make the connection ?

 

I also think you did not get my problem clearly. When SW1 SW0 ate both turned up, I see the input source connected to J3 on both the output displays. So displays are getting all the info. But when I turn both SW1 SW0 down(for the input source connected to J1) , I see nothing on both the output displays. But the input souce connected to J1 is correct beacuse when I connected this source to connector J3, I got output on both displays.

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eteam00
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Registered: ‎07-21-2009

Please do not attach entire documents which

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joelby
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Registered: ‎10-05-2010

I think that JP2 is the 2x2 header right next to J1. It is supplied with two jumpers, but from memory they are configured incorrectly when delivered from the factory, shorting the SDA and SCL lines together.

 

Note that the reference design doesn't do anything to switch these control lines along with the video displays, and I'm not sure how you would do that correctly when driving two displays from one source. If you search this forum, you'll see that many people have had trouble with this design, so don't be too discouraged if you find that it doesn't quite work as you'd expect.

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saurabh_daimler
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Registered: ‎11-02-2011

@joelby - I found JP2. I just gave you an example when I told you about driving two displays from one source. If I see one source on one display and the other source on the other display, thats perfectly fine ! But I can not see that. Let say when SW1 is up and SW0 is down, I see output on one display and the other has nothing on it. This is beacuse JP2 is not configured correctly.

 

But I have to get this running as this is the requirement of my project. I have to deal with two input video sources and get two outputs.  I found this in the AtlysGeneral.ucf provided on the digilent website:

 

# onboard HDMI OUT

NET "HDMIOUTSCL" LOC = "D9"; # Bank = 0, Pin name = IO_L34P_GCLK19, Sch name = TMDS-TX-SCL

NET "HDMIOUTSDA" LOC = "C9"; # Bank = 0, Pin name = IO_L34N_GCLK18, Sch name = TMDS-TX-SDA

 

# onboard HDMI IN1 (PMODA)

NET "HDMIIN1SCL" LOC = "C13"; # Bank = 0, Pin name = IO_L50P, Sch name = PMOD-SCL

NET "HDMIIN1SDA" LOC = "A13"; # Bank = 0, Pin name = IO_L50N, Sch name = PMOD-SDA

 

# onboard HDMI IN2

NET "HDMIIN2SCL" LOC = "M16"; # Bank = 1, Pin name = IO_L47P_FWE_B_M1DQ0, Sch name = TMDS-RX-SCL

NET "HDMIIN2SDA" LOC = "M18"; # Bank = 1, Pin name = IO_L47N_LDC_M1DQ1, Sch name = TMDS-RX-SDA

 

Simly copying and pasting it in dvi_demo.ucf for xapp495 provided in xilinx doesn't work. How should I write these lines in dvi_demo.ucf ? Or is there any other way of getting the output ?

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joelby
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Registered: ‎10-05-2010

I don't think XAPP495 does anything to switch SCL/SDA. You can't just add them to the UCF without providing additional logic in HDL to deal with them. This should be pretty straightforward, though. I'm also not quite sure what you do in the case where two monitors are connected to the same video source - which of the two monitors would you route to the source? Does the other monitor care if its EDID isn't respected? Maybe it'll work - it might be worth a try.

 

Did you try fixing the JP2 configuration? Because the SCL/SDA is just passed through from the input to the adjacent output connector, I imagine these shennanigans might only work reliably when both video sources are the same type and set to the same resolution, and both monitors are identical.. but that's just a guess given my lack of experience with HDMI.

 

I'd investigate, perhaps using ChipScope Pro, whether video is actually being sent out both ports when you expect it to be. As always, it's tricky to know what's going on without getting your hands dirty in the code and debugging, and because different video sources and sinks may make different assumptions about what they're connected to, no-one else can replicate your setup precisely. Also, you can never trust that the a reference design will do exactly what you want it to do under all circumstances. XAPP495 seems to be a particularly problematic one!

 

saurabh_daimler
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Registered: ‎11-02-2011

@joelby - Solved it ! :) :)

 

Problem was JP5 for connector J1.  JP5 is connected to ground on one end and not(OE) at the other. If I leave JP5 open, not(OE) gets the input 1 from VCCV3 resulting in no display for input source connected to J1. Therefore, JP5 should never be open. See the atlys schematic page 2 for more info.

 

Since I am using a display emulator, SCL and SDA info is given by the emulator also. But in general, JP2,6,7 should not be open in order to pass the SCL, SDA to the output. Now all get all the possible outputs on 2 displays.

 

SW1    SW0       Display1           Display2

0           0             source_J1        source_J1

0           1             source_J1        source_J3

1           0             source_J3        source_J1

1           1             source_J3        source_J3

 

where source_J1 = input source connected to connector J1, source_J3 = input source connected to connector J3, OE = output enable

 

Thanks a lot for your help !!

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joelby
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Registered: ‎10-05-2010

Great catch! I'd never even noticed JP5 before. Maybe someone should re-write the reference manual and include this sort of critical information?

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rdemirci
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Registered: ‎02-19-2013

Hi,

 

Are there any testbenches for xapp495?

 

Thanks,

Rifat

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