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Visitor nick1111
Visitor
662 Views
Registered: ‎04-16-2018

CCLK pin in the Master and Slave Serial configuration

Hi all.
I've an old custom board with the SPARTAN-6 XC6SLX9 and the XCF04S. In the board there was a PIC18F87J10 microcontroller.
With small modification, is it possible to modify the board so that the microprocessor can configure the FPGA?
My big doubt is with the "CCLK pin" because in the new revision I'd have "Master Serial" so that the FPGA could be configured by the XCF04S and "Slave Serial" so that the microcontroller can configure the FPGA.
If this configuration is possible, could anyone suggest me some documentation?
Thanks.

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4 Replies
Contributor
Contributor
636 Views
Registered: ‎04-04-2018

Re: CCLK pin in the Master and Slave Serial configuration

Should be possible. You need to be able to change the mode pins. You should also be able to bit-bang the bitstream to serial data and CCLK on PIO pins. You also need to make sure that the XCF04S part and processor are not trying to at the same time.

 

Look at the Spartan6 configuration guide. Serial modes start on page 23.

 

https://www.xilinx.com/support/documentation/user_guides/ug380.pdf 

Steve Markgraf - Sr. FPGA Design and Support Engineer
www.designlinxhs.com
Visitor nick1111
Visitor
616 Views
Registered: ‎04-16-2018

Re: CCLK pin in the Master and Slave Serial configuration

Thank you for the answer.
I read the ug380 and so in my case I should switch the CLK signal: when I need to use the XCF04S the CLK comes from the FPGA to the PROM, whereas when I need to use the microcontroller to configure the FPGA, the CLK signal comes from the micro to the FPGA. Is this advisable? For example, could I switch this line with DIP-SWITCH?

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605 Views
Registered: ‎06-21-2017

Re: CCLK pin in the Master and Slave Serial configuration

Can you tri-state the CCLK pin on the PIC based on the mode bit that controls master/slave serial configuration?  That would give you one fewer bits to run to a switch.  You probably need to figure out how to do this with the data bit anyway.  Two things:

1. CCLK will be fairly sensitive to ringing.  You will need a clean signal. 

2. Do you have enough memory attached to your PIC to hold an FPGA bit file?

 

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Visitor nick1111
Visitor
588 Views
Registered: ‎04-16-2018

Re: CCLK pin in the Master and Slave Serial configuration

Ok, thanks for the suggestions.
The CCLK signal will come from the PIC like as it is possible to see in the DIGILENT boards.
About the second point, I'm thinking to program the FPGA directly by USB->NET2272->PIC->FPGA, and so the PIC doesn't hold the program inside.

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