UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer jeffzhang
Observer
2,715 Views
Registered: ‎11-03-2010

Does Spartan6 ISERDES2 support DDR mode?

Hi,

 

I am leaning Spartan6 device. in UG381 (Spartan6 SelectIO user guide), it mentioned there are three clock inputs for ISERDES2, CLK0, CLK1 and CLKDIV. CLK1 is "only used when the clock doubler is engaged(see DATA_RATE attribute)" as this document says. I checked DATA_RATE description. it has SDR and DDR value to select. But I can't find any information regarding how ISERDES2 been used under DDR mode.

My question is,

what is the case that CLK1 involved?

Does ISERDES2 support DDR mode?

if yes, what is internal connection for CLK1 or CLK0?

 

Regards,

Jeff

0 Kudos
1 Reply
Teacher eteam00
Teacher
2,704 Views
Registered: ‎07-21-2009

Re: Does Spartan6 ISERDES2 support DDR mode?

in UG381 (Spartan6 SelectIO user guide), it mentioned there are three clock inputs for ISERDES2, CLK0, CLK1 and CLKDIV. CLK1 is "only used when the clock doubler is engaged(see DATA_RATE attribute)" as this document says. I checked DATA_RATE description. it has SDR and DDR value to select. But I can't find any information regarding how ISERDES2 been used under DDR mode.

ISERDES2 operating in DDR mode is, as you have discovered, woefully underdocumented.  Don't expect great improvements any time soon.  The much more widely useful SDR operating mode, while better documented, is still suffering from glaring omissions and even misrepresentations in the documentation.  Hopefully this thread can shiine some light on the DDR operating mode for those who - like you - are too persistent or stubborn to stay away.

 

Sanity check:  ISERDES2 DDR vs SDR

  • DDR mode does not provide double the performance (bit rate) of SDR mode (See DS162 Table 25).
  • DDR mode merely supports a half-rate input clock, and that is its largest (and possibly only) advantage.
  • DDR mode has limited de-serialisation rate options.  In SDR mode, deserialisation up to 1:8 is straightforward.  For larger word widths, SDR supports 1:10, 1:12, 1:14, and 1:16 with the final 1:2 deserialisation performed in the FPGA fabric.  Using DDR mode, 1:10 and 1:14 are not possible.

Clock generation

See UG382 (v1.4) Figure 1-15 for the essential diagram of how to generate the ISERDES2 CLK0 + CLK1 input clocks, as well as the CLKDIV and SERDESSTROBE signals.  Also refer to UG382 Figure 1-35.  If you are going to be using a PLL for multiplying an input clock up to bit-rate clock, there is absolutely no useful purpose for operating the ISERDES2 blocks in DDR mode.

 

More applications information

In the absence of ground-up descriptions of DDR operation, there is XAPP1064 (PDF and ZIP archive found here).  In this set of ISERDES2 and OSERDES2 design examples are several examples of ISERDES2 operating in DDR mode, including clock generation and distribution.  You have the choice of using one of the example designs with few modifications -- accepting more or less on faith that the design is correct -- or using the explicit and implicit inferences of the design examples to try to impute and deduce and conjure a more fundamental personal understanding of how DDR mode works.  In either case, you won't find much help in the documentation if your design doesn't work; you will likely need support from Xilinx to troubleshoot your design.

 

In case of apps support

If you do need apps support help in this area, be sure to try any proposed explanations or corrections as qiuckly as possible.  The thin documentation of ISEREDS2 DDR mode may lead to poorly informed responses from apps folks who may not dig deep enough into the under-documented details of the circuits.  It's an area of design which is susceptible to "not knowing what you don't know" type errors.  On a subject so demanding of detail, it is critical that you and the support engineer have tightly matched understandings of the design problems and solutions.  Misaligned understandings - between you and the Xilinx support engineer - are hard to avoid, but they must be avoided.

Does ISERDES2 support DDR mode?

Yes.

if yes, what is internal connection for CLK1 or CLK0?

See the referenced sections of UG382 referenced above, plus the XAPP1064 examples.


Xilinx is quite reticent about describing inner workings of their blocks, perhaps with some justification.  The logic in some of these blocks has been heavily optimised and cost-reduced, and perhaps the resulting circuits defy simple and concise explanations and descriptions.  Your best bet is to carry on a private discussion with someone with "insider" insight to the "under the hood" workings.

 

In summary:

  • Documentation for ISERDES2 DDR mode is sparse and somewhat disjoint.  See XAPP1064 and UG382 to fill in some blanks.
  • DDR mode is more limited than SDR mode in some important ways: missing ratios and thinner support/docs.
  • DDR mode does not support higher serial bit rate than SDR.

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.