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Hardware Calibration Fail for SLX45T + 4-Gbit DDR3 DRAM

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Visitor
Posts: 16
Registered: ‎03-29-2013

Hardware Calibration Fail for SLX45T + 4-Gbit DDR3 DRAM

Hello!

 

I've developed PCB with SLX45T and MT41K256M16HA-125:E. The DRAM chip has 4 Gbit capacity, so the part was manually created within MIG and based on supported MT41K128M16HA-125:E (this DDR3L chip it is equivalent to MT41J128M16HA, which is normal DDR3).

 

I use normal MIG example project (modified for 50 MHz clock source) and I ran into calibration problem - calib_done does not go high. As I discovered, calibration stucks at WAIT_FOR_UODONE state. Chipscope shows MCB_UODONECAL is always low - please check the picture attached.

 

As to PCB itself - it was made according to all constraints, it has 13 layers, gold plating, impedance is checked by manufacturer, so on. I've also made PCB for XC6SLX9-3FTG256C and MT41K128M16 just before. It works great and have no calibration problems at all. That PCB uses the same 50 MHz clock source too.

 

I can't find any detailed info about MCB hardware calibration.

Does anyone have ideas about reason of the fault? What should I check on the next step?

 

Many thanks for any help!

With regards,

Maksim

Stuck on 0x28.png

Moderator
Posts: 26
Registered: ‎05-02-2017

Re: Hardware Calibration Fail for SLX45T + 4-Gbit DDR3 DRAM

hi @kotnitro ,

 

is it possible to share the schematic or connection between you're FPGA and DDR3 ,Source of Calibration Delay Values

Visitor
Posts: 16
Registered: ‎03-29-2013

Re: Hardware Calibration Fail for SLX45T + 4-Gbit DDR3 DRAM

Calibration values go from regular soft calibration procedure without any changes.

And FPGA-to-DRAM schematic is attached, please check.

FPGA-DRAM.png

Moderator
Posts: 26
Registered: ‎05-02-2017

Re: Hardware Calibration Fail for SLX45T + 4-Gbit DDR3 DRAM

hi @kotnitro,

 

i have gone through  you're   connectivity for FPGA and RAM , seem to be good are the values of resistance and cap are in line with BOM , please check once following for more debugging .

 

https://www.xilinx.com/support/answers/43537.html

 

https://www.xilinx.com/support/answers/43557.html

 

thanks 

 

Sekhar 

Visitor
Posts: 16
Registered: ‎03-29-2013

Re: Hardware Calibration Fail for SLX45T + 4-Gbit DDR3 DRAM

Thank you, @csattar

Passive elmenents' values are correct.

I checked some signals with oscilloscope, unfortunately, it is not good enough to judge about exact waveform, only about signal presence.

As I see, DRAM_CK/#DRAM_CK pair is OK, #DRAM_RESET is high, but there is no activity on LDQS/UDQS, Address or Data lines, only some constant voltage values, which depend on MCB Reset button state.

 

On my previous board (which is mentioned at the top message), I see activity on those lines with the same oscilloscope.

 

Hardware calibration itself performs DQS centering using data pattern writing and reading, but there are no activity address and data lines. It looks like MCB hardware calibration does not start at all for some reason.

Is there any way to judge about a step, where hardware calibration stucks? Any status signals, flags, etc.?

 

With regards,

Maksim

Moderator
Posts: 26
Registered: ‎05-02-2017

Re: Hardware Calibration Fail for SLX45T + 4-Gbit DDR3 DRAM

Hi @kotnitro,

 

When calib_done does not assert, which signifies a calibration failure, it is important to first identify which stage of calibration failed.TheSpartan-6 MCBFPGA design goes through the following calibration stages:

  • Input TerminationCalibration
  • DQS Centering
  • Read WindowCalibration
  • Continuous DQS Tuning

These steps assume the Example Design with the debug port is running in your hardware. If this design is not loaded in your hardware, please refer to (Xilinx Answer 43520).

For information on Calibrated Input Termination Debug, see (Xilinx Answer 42176).

For information onDQS CenteringDebug, see (Xilinx Answer 43643).

For general information on usage of the debug port, see (Xilinx Answer 43539).

 

Regrads

 

S.chandra sekhar 

 

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Visitor
Posts: 16
Registered: ‎03-29-2013

Re: Hardware Calibration Fail for SLX45T + 4-Gbit DDR3 DRAM

@csattar

as you remember, we are stucked here at state 7'h28 (mcb_soft_calibration.v)

 

START_DYN_CAL_PRE:  begin   // 7'h27
          LastPass_DynCal <= `IN_TERM_PASS;
          MCB_UICMDEN     <= 1'b0;    // release UICMDEN
          MCB_UIDONECAL   <= 1'b1;    // release UIDONECAL - MCB will now initialize.
          Pre_SYSRST      <= 1'b1;    // SYSRST pulse
          if (~CALMODE_EQ_CALIBRATION)      // if C_MC_CALIBRATION_MODE is set to NOCALIBRATION
            STATE       <= START_DYN_CAL;  // we'll skip setting the DQS delays manually
          else if (pre_sysrst_minpulse_width_ok)   
            STATE       <= WAIT_FOR_UODONE;
          end
        WAIT_FOR_UODONE:  begin  //7'h28
          Pre_SYSRST      <= 1'b0;    // SYSRST pulse
          if (IODRPCTRLR_RDY_BUSY_N && MCB_UODONECAL) begin //IODRP Controller needs to be ready, & MCB needs to be done with hard calibration
            MCB_UICMDEN <= 1'b1;    // grab UICMDEN
            DQS_DELAY_INITIAL <= Mult_Divide(Max_Value, DQS_NUMERATOR, DQS_DENOMINATOR);
            STATE       <= LDQS_WRITE_POS_INDELAY;
          end
          else
            STATE       <= WAIT_FOR_UODONE;

Within WAIT_FOR_OUDONE we have MCB_UICMDEN == 1'b0, so user interface is blocked and the MCB is under control of internal calibration block until that internal calibration finished. Please correct me, if I'm wrong.

Are you sure, that debug port can provide any helpful data while MCB hardware calibration stucks?

 

Thank you!

With regards,

Maksim

 

Visitor
Posts: 16
Registered: ‎03-29-2013

Re: Hardware Calibration Fail for SLX45T + 4-Gbit DDR3 DRAM

The important sign of the current fault - there is no activity on LDQS/#LDQS and UDQS/#UDQS lines. MCB hardware calibration should involve those signals into the calibration process (I see it on my previous board).

Unfortunately, these signals go from blackboxed MCB and IODRP2, so I can't check what's wrong.

It looks like hardware calibration does not really begins (as we see no attempts to put anything to xDQS).

 

Maybe Xilinx employees could give some ideas about that "stucked" MCB mode?

 

Many thanks for any help!

With regards,

Maksim