We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Internet Explorer 11,
Safari. Thank you!
I'm doing a project with Spartan6 and two DDR2 SDRAM Memories. I've already implemented all my code for writing data to the memory and for reading. I've also done the simulation of this code. Now I wanted to include the MIG 3.7 Core in my ISE 13.1 Project.
After adding the core with Core generator and including the code for instantiation, I wanted to synthesize my project. But now I always gets the following message in Console window:
Regenerate Core - MEM: All required files are available.
Process "Regenerate Core" failed
There is no additional Error or Warning, just this output. What's the reason for this problem? My idea was that it's maybe a wrong project setting. But without error messages it's difficult to find out. I hope someone here knows the problem already and could help me.