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313 Views
Registered: ‎01-21-2019

ADC, How to resolve this error

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Implementing ADC

entity ADC_8_bit is
  port (analog_in : in real range -15.0 to +15.0;
        digital_out : out std_logic_vector(7 downto 0)
       );
end entity;

 getting error

ERROR:HDLParsers:847 - "C:/Users/Ashish/Desktop/Thesis/Arpita GS ADC/New folder/Arpita1/ad.vhd" Line 36. The type of the range constraint is not compatible with real.


ERROR:HDLParsers:808 - "C:/Users/Ashish/Desktop/Thesis/Arpita GS ADC/New folder/Arpita1/ad.vhd" Line 78. ADC_8b_10v_bipolar can not have such operands in this context.

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Moderator
Moderator
183 Views
Registered: ‎03-16-2017

Re: ADC, How to resolve this error

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Hi @ashishsoni15,

 

Let me know if you have further queries on this thread, or you can close this thread by marking it accepted solution.

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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6 Replies
272 Views
Registered: ‎06-21-2017

Re: ADC, How to resolve this error

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@ashishsoni15What are you trying to do?  Unless your FPGA has a built in ADC, in the Xilinx case a System Monitor, you don't have an analog input.  What FPGA are you working with? 

258 Views
Registered: ‎01-21-2019

Re: ADC, How to resolve this error

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I am implementing using vhdl as a part of my project.

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Moderator
248 Views
Registered: ‎03-16-2017

Re: ADC, How to resolve this error

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Hi @ashishsoni15,

 

Please upload the source code to regenerate this error at our end to debug it. 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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225 Views
Registered: ‎01-21-2019

Re: ADC, How to resolve this error

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library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
  use ieee.math_real.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;


entity ADC_8_bit is
  port (analog_in : in real range -15 to 15;
        digital_out : out std_logic_vector(7 downto 0)
       );
end entity;

architecture original of ADC_8_bit is

  constant conversion_time: time := 25 ns;

  signal instantly_digitized_signal : std_logic_vector(7 downto 0);
  signal delayed_digitized_signal : std_logic_vector(7 downto 0);

  function ADC_8b_10v_bipolar (
    analog_in: real range -15.0 to +15.0
  ) return std_logic_vector is
    constant max_abs_digital_value : integer := 128;
    constant max_in_signal : real := 10.0;
    variable analog_signal: real;
    variable analog_abs: real;
    variable analog_limited: real;
    variable digitized_signal: integer;
    variable digital_out: std_logic_vector(7 downto 0);
  begin
    analog_signal := real(analog_in);
    if (analog_signal < 0.0) then    -- i/p = -ve
      digitized_signal := integer(analog_signal * 12.8);
      if (digitized_signal < -(max_abs_digital_value)) then
        digitized_signal := -(max_abs_digital_value);
      end if;
    else    -- i/p = +ve
      digitized_signal := integer(analog_signal * 12.8);
      if (digitized_signal > (max_abs_digital_value - 1)) then
        digitized_signal := max_abs_digital_value - 1;
      end if;
    end if;
    digital_out := std_logic_vector(to_signed(digitized_signal, digital_out'length));
    return digital_out;
  end ADC_8b_10v_bipolar;

begin

  s0: instantly_digitized_signal <=
        std_logic_vector (ADC_8b_10v_bipolar (analog_in));

  s1: delayed_digitized_signal <=
        instantly_digitized_signal after conversion_time;

  s2: digital_out <= delayed_digitized_signal;

end original;

I am getting error in defining analog input i.e.

port (analog_in : in real range -15 to 15;

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Moderator
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217 Views
Registered: ‎03-16-2017

Re: ADC, How to resolve this error

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Hi @ashishsoni15,

The issue is here : 

  s0: instantly_digitized_signal <=
        std_logic_vector (ADC_8b_10v_bipolar (analog_in));

Real Literal: A real number may be positive or negative, but must be written with a decimal point. 

Synthesis tool does not support inferred floating point arithmetic from the real type. You need to open CoreGen or IP catalogue from within Xilinx ISE or Vivado, and use this to generate the floating point functions that you need.

Though the code is not synthesizable(showing synthesis error), it can be used for simulation.Not synthesisable means cannot be burnt into an fpga kit. Simulation of this code will give no error. 

 

 

 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
Moderator
Moderator
184 Views
Registered: ‎03-16-2017

Re: ADC, How to resolve this error

Jump to solution

Hi @ashishsoni15,

 

Let me know if you have further queries on this thread, or you can close this thread by marking it accepted solution.

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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