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toxup_1
Adventurer
Adventurer
6,296 Views
Registered: ‎02-12-2016

AREA_GROUP constraint for a selection of primitives

In the pursuit of decreased routing delay (90%), I am attempting to manually place pblocks in Planahead 14.7.

First:

I did try to quickly place component-level pblocks but without success.

As I have understood, these should not be too big and so I will try to make them smaller.

 

Specifically, I want to collect multiple primitives into one area_group. However, when doing this with Planahead and selecting primitives I end up with ~5k individual pblocks.

 

Is there a way to select multiple primitives or is the only way of obtaining fine-granular pblocks to split RTL?

 

Thanks!

 

Selection_087.bmp
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toxup_1
Adventurer
Adventurer
5,914 Views
Registered: ‎02-12-2016

Is there anyway of obtaining basic knowledge about manual placement of components in Planahead without attending an advanced FPGA design course in another country next year?

 

A clarification on the following subjects would be highly appreciated:

1. General placement strategies. (how small pblocks should be, if the size of pblocks are limited to vhdl entities or can they be split?)

2. How to clearly spot poor placement solutions in Planahead. The "routing resources" button which is suggested here: 

https://forums.xilinx.com/t5/Timing-Analysis/placement-routing-delay/td-p/627481

is not visible in my Planahead 14.7.

 

The attached picture displays the most critical path and the longest delays are through what looks like the shorted paths and some super long ones are adding minimal delay. 

 

Selection_088.bmp
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