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Anonymous
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6,970 Views

AXIStream to Video Out IP Core output is zero

I am working on processing PAL (720 X 576 interlaced video) video. Initially, I have a design (#1 shown below).This design works good and I am able to view the output, i.e., whatever is captured by camera, without any processing (only PAL decoder to PAL encoder, video displayed on monitor)

 

Next, I tried to convert it to AXIstream and convert back to video (as shown in design #2). This design gives all outputs of AXIS to Video out block (including dec_out[7:0]) as zeros (when viewed on ILA). PAL monitor looks all black.

 

Posted.png

 

How can I fix this?

 

vid_io_out_clk is the pixel clock which I get from PAL decoder (27MHz).

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8 Replies
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Anonymous
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6,962 Views

Re: AXIStream to Video Out IP Core output is zero

Try setting Video out to master/salve, also try connecting vtg_ce to axis_enable. Probe the signals on the output and see if synchronization signals are present. Also check the "locked" signal. This indicates if the video out is synchronized with the video in. All the configs in the IP are correct?

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Anonymous
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Re: AXIStream to Video Out IP Core output is zero

Thank you. Yes, I have tried to change Master to Slave (of AXIS to video out block). There are no synchronization signals present. I have also added a clocking wizard....which outputs 27MHz too. The output syncs are all zero. I have also tried to connect vtg_ge (of axi in to video out) to axis_enable (of video in to axis). Output is still blank.

 

1. How can I view if it is locked? If I am not getting video (or sync signals), it means it isn't locked. Right?

 

2. Please note that the output on monitor is complete black except for a thin white line towards the bottom. (around line number 450 or so)

 

3. The encoder requires active low hsync and vsync pulses.

 

Untitled.png

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Anonymous
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6,936 Views

Re: AXIStream to Video Out IP Core output is zero

Try adding video timing controller.
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Xilinx Employee
Xilinx Employee
6,916 Views
Registered: ‎08-02-2011

Re: AXIStream to Video Out IP Core output is zero

Yes, for this setup (common clock), you should add a VTC in generator mode and then connect the vtg_ce signal from the vid_out core to the vtc. The Vid Out core should be in slave mode.

 

 

www.xilinx.com
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Anonymous
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6,892 Views

Re: AXIStream to Video Out IP Core output is zero

We have tried adding VTC too.

 

I am not getting any output after Video In to AXIS out IP Core. It is all zero. So the problem lies with VideoIn to AXIS out itself.

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Anonymous
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Re: AXIStream to Video Out IP Core output is zero

Then try to use additional VTC IP and connect its timing output to the VideoIN timing input. Do not connect your external signals. Provide some constant value to the VideoIN data so you know it is not zero. and try to get your system running. If it works then try using your external sync signals instead of the fist VTC. Also, to start with, I would suggest to use the external video data clock for all the blocks.

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Anonymous
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Re: AXIStream to Video Out IP Core output is zero

Hello,

 

Thanks for your reply.

 

I have noticed another point.  In the design above, if we connect VDMA to VideoInAXISout block, I can see data on the video_out signal (of VideoInAXISout). If not, we do not get any data at this pin. Is there anything we are missing out?

 

Is there a reason why I should use external video data clock for all the blocks? You mean the clock from decoder, right?

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Anonymous
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Re: AXIStream to Video Out IP Core output is zero

I do not know how is your system set up. I would suggest to drive all the blocks with the pixel clock from your video source (only to get the system working). This way, you know for sure that your system is in sync.

The VDMA writes to memory and therefore, does not halt the VideoIn block, however, some of the blocks downstreem can not synchronize with the input block, or are not working properly and, therefore, send 'not ready' axis signal to the VideoIN block.

I would suggest to make your system work without the external input first. Get a test pattern generator and have it output on the screen. Then you can add the VideoIn block and drive its timing signals with additional video timing controller and have it pass through the tpg. Once this works, you can try to replace the vtc with your video source.