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Visitor wangjiayu
Visitor
1,594 Views
Registered: ‎11-06-2017

Abnormal program termination (11)

I have a question when i synthesis a project ,vivado 2016.4 crashed.

 

INFO: [Synth 8-638] synthesizing module 'DW_axi_busmux__parameterized105' [/home/jywang/fpga_a7/src/verilog/axi/DW_axi.lst.v:97559]
 Parameter BUS_COUNT bound to: 5 - type: integer
 Parameter MUX_WIDTH bound to: 75 - type: integer
 Parameter SEL_WIDTH bound to: 3 - type: integer
Abnormal program termination (11)
Please check '/home/jywang/fpga_a7/top/top/top.runs/synth_1/hs_err_pid7806.log' for details
Parent process (pid 7806) has died. This helper process will now exit

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7 Replies
Moderator
Moderator
1,582 Views
Registered: ‎09-15-2016

Re: Abnormal program termination (11)

Hi @wangjiayu,

 

Which OS are you using?

Can you try setting module 'DW_axi_busmux__parameterized105' as top if possible and run synthesis again to see if crash is possible? Do you have a test case that you can share in community?

 

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Moderator
Moderator
1,551 Views
Registered: ‎05-31-2017

Re: Abnormal program termination (11)

Hi @wangjiayu,

 

Have you tried to synthesize the design using different strategies ?

If so, Are you facing the same Abnormal Termination(11) while using different strategies ?

Is this a random crash ?

 

Thanks & Regards,

A. Shameer.

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Xilinx Employee
Xilinx Employee
1,419 Views
Registered: ‎07-21-2014

Re: Abnormal program termination (11)

Hi,

Crash happens during elaboration stage itself while binding parameter.
Will it be possible to share your project file?

-Shreyas
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Newbie thodoe
Newbie
1,268 Views
Registered: ‎01-19-2018

Re: Abnormal program termination (11)

Hi Guys,

 

I have the problem Abnormal program termination (11) in synthesis step with vivado 2017.2 when i have

the pcie core included in design.

 

The design was already running with PCIe but now it doesn't work. The design without PCIE works fine but not together.

 

Stack:
/lib/x86_64-linux-gnu/libc.so.6(+0x354b0) [0x7fb959d3a4b0]
/opt/Xilinx/Vivado/2017.2/lib/lnx64.o/librdi_synth.so(TGenDelayArc::computeDelayAndSlew(TNInstC*, TGenC const*, BRFTime&, RF<TTimeShort>&, bool, RF<TTimeShort>, bool, bool) const+0x289) [0x7fb91f579e99]
/opt/Xilinx/Vivado/2017.2/lib/lnx64.o/librdi_synth.so(TGenDelayArc::delay(TNInstC*, bool, TGenC const*, bool, bool) const+0x1b7) [0x7fb91f57a4d7]
/opt/Xilinx/Vivado/2017.2/lib/lnx64.o/librdi_synth.so(TGenDelay::writeTimingArc(_IO_FILE*, UStrBuf, UStrBuf, TNGenC*, TNInstC const*) const+0x14b) [0x7fb91f57287b]
/opt/Xilinx/Vivado/2017.2/lib/lnx64.o/librdi_synth.so(TGenPinBase<TGenDelaysArray>::writeTimingArc(_IO_FILE*, UStrBuf, int, TNGenC*, TNInstC const*) const+0x1b1) [0x7fb91f575c81]
/opt/Xilinx/Vivado/2017.2/lib/lnx64.o/librdi_synth.so(TGenC::writeTimingArc(TNInstC const*, char*) const+0x1a0) [0x7fb91f5747c0]
/opt/Xilinx/Vivado/2017.2/lib/lnx64.o/librdi_synth.so(TNInstC::tCreate()+0x1ee) [0x7fb91f59b5be]
/opt/Xilinx/Vivado/2017.2/lib/lnx64.o/librdi_synth.so(TNInstC::cacheDelay(int, int, int, BRFTime&, bool)+0x114) [0x7fb91f59e1e4]
/opt/Xilinx/Vivado/2017.2/lib/lnx64.o/librdi_synth.so(TGenDelayArc::computeDelayAndSlew(TNInstC*, TGenC const*, BRFTime&, RF<TTimeShort>&, bool, RF<TTimeShort>, bool, bool) const+0x1e8) [0x7fb91f579df8]
/opt/Xilinx/Vivado/2017.2/lib/lnx64.o/librdi_synth.so(TGenPin::updateDrvArcs(TNInstC*, bool, TGenC*, bool)+0x886) [0x7fb91f57c806]
/opt/Xilinx/Vivado/2017.2/lib/lnx64.o/librdi_synth.so(TNInstC::updateDrvArcs(int, bool, bool)+0xf9) [0x7fb91f59fe49]
/opt/Xilinx/Vivado/2017.2/lib/lnx64.o/librdi_synth.so(TNPinC::updateDrvArcs(bool, bool)+0x55) [0x7fb91f5b1425]
/opt/Xilinx/Vivado/2017.2/lib/lnx64.o/librdi_synth.so(TNPinC::updateDriverAndLoadingPins(int, TNetInfo&, bool)+0x17a) [0x7fb91f5b180a]
/opt/Xilinx/Vivado/2017.2/lib/lnx64.o/librdi_synth.so(TNPinC::updateDriverAndNetArcs(bool)+0x133) [0x7fb91f5bb993]
/opt/Xilinx/Vivado/2017.2/lib/lnx64.o/librdi_synth.so(TNPinC::slew(TBiIn)+0x21e) [0x7fb91f5bc8de]

 

 

Who can help me to fix that.

 

Thanks

 

Christoph

 

 

 

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Xilinx Employee
Xilinx Employee
1,257 Views
Registered: ‎02-16-2014

Re: Abnormal program termination (11)

Hi @thodoe

 

Can you share the vivado.log file?

Did you get a chance to synthesize this design in latest vivado 2017.4?

If you can provide testcase that will help me to further investigate this issue.

 

 

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Newbie thodoe
Newbie
1,247 Views
Registered: ‎01-19-2018

Re: Abnormal program termination (11)

Hi yes please find attached the file,

yes we have tried to check this with 2017.4 but it is the same result. The point is, that this

issue occurs since last RTL design changes ... that means it has to work and there must be an issue in

combination with the PCIe

 

Thank your very much for short response :-)

 

 Thomas

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Xilinx Employee
Xilinx Employee
1,190 Views
Registered: ‎02-16-2014

Re: Abnormal program termination (11)

Hi @thodoe

 

Can you share the project with me?

If you can share project, I will send you ezmove link where you can upload files.

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