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Visitor
Visitor
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Registered: ‎01-16-2009

Adder and Shifter using Blocking and non-Blocking Assignments

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My Question is related to synthesizes of my Verilog Code below is a module names as addshifter which when synthesis just make a shifter. please note i have used non-blocking statements. but the code shows that I am making a adder first and then a shifter that will shift the values of Areg. Now If I replace the non-blocking statement with the blocking statements. the Synthesizes tools makes an adder 4-bit and a 4-bit register shifter.

 I want to ask why is this so.... I could not fiqure it out why it works well with blocking assignments and not with non-blocking assignments. This was a test program I made to check. I was having a same problem while i was coding a multiplier of the add & shift type. 

 

module addshifter(A,B,clk,rst)

 

input [3:0] A;

input clk,rst;

output [3:0] B;

reg [3:0] Areg;

 

assign B = Areg;

 

always @ (posedge clk or posedge rst)

begin

   if(rst)

       Areg <= A;

   else

       Areg <= Areg +1;

       Areg <= Areg <<1;

end

endmodule 

 

 

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Voyager
Voyager
5,792 Views
Registered: ‎08-30-2007

Re: Adder and Shifter using Blocking and non-Blocking Assignments

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The Verilog code is doing the proper action for a non-blocking assignment.  If you look at the

Verilog spec, the last non-blocking assignment in a block wins.  Thus

 

always @(posedge clk)

  begin

  A <= 1;

  A <= 0;

  end

 

will correctly assign the value of 0 to A both in simulation and synthesis.  Why?  Because for non-blocking,the last

assignment wins. Verilog performs the following operations at each time step:

  a) evaluate the Right Hand Side (RHS) of all non-blocking assignments and save the results in temporary variables.

  b) assign the temporary variables to the final variables.

This is a simplification, but gives you the general idea as to what is going on.

 

This method insures that operations like:

  always @(posedge clk)

    begin

    A <= 0;

    B <= A;

    C <= B;

    D <= C;

    end

operate correctly.   Try simulating the above logic both with blocking & non-blocking assignments.  When you

understand why the two assignment styles work differently, you'll understand why your example works the

way it does.

 

A simple rule of thumb that many people follow *most* of the time is

   "always use non-blockig assignment in sequential (clocked) logic"

   "always use blocking assignments in  combinatorial logic"

but... rules are meant to be broken sometimes!

 

I hope this helps.  You really need to understand this fundamental the reason for the 2 different assignment styles.

 

John Providenza

 

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Voyager
Voyager
5,793 Views
Registered: ‎08-30-2007

Re: Adder and Shifter using Blocking and non-Blocking Assignments

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The Verilog code is doing the proper action for a non-blocking assignment.  If you look at the

Verilog spec, the last non-blocking assignment in a block wins.  Thus

 

always @(posedge clk)

  begin

  A <= 1;

  A <= 0;

  end

 

will correctly assign the value of 0 to A both in simulation and synthesis.  Why?  Because for non-blocking,the last

assignment wins. Verilog performs the following operations at each time step:

  a) evaluate the Right Hand Side (RHS) of all non-blocking assignments and save the results in temporary variables.

  b) assign the temporary variables to the final variables.

This is a simplification, but gives you the general idea as to what is going on.

 

This method insures that operations like:

  always @(posedge clk)

    begin

    A <= 0;

    B <= A;

    C <= B;

    D <= C;

    end

operate correctly.   Try simulating the above logic both with blocking & non-blocking assignments.  When you

understand why the two assignment styles work differently, you'll understand why your example works the

way it does.

 

A simple rule of thumb that many people follow *most* of the time is

   "always use non-blockig assignment in sequential (clocked) logic"

   "always use blocking assignments in  combinatorial logic"

but... rules are meant to be broken sometimes!

 

I hope this helps.  You really need to understand this fundamental the reason for the 2 different assignment styles.

 

John Providenza

 

View solution in original post

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