Adding signal to sensitivity list ruins the synthesis

[vivadouser67]

I'm writing a simple D-flip-flop in Verilog and looking at what it synthesizes to. Here's what I have:

module d_flip_flop(
    input d,
    input clr,
    input clk,
    input ce,
    output reg q
);

always @(posedge clk) begin: d_flip_flop
    if (clr) begin
        q <= 1'b0; 
    end else if (ce) begin
        q <= d;
    end
end

endmodule

And it synthesizes to:

However, making this change to the code and adding CE to the sensitivity list:

module d_flip_flop(
    input d,
    input clr,
    input clk,
    input ce,
    output reg q
);

always @(posedge clk or posedge ce) begin: d_flip_flop
    if (clr) begin
        q <= 1'b0; 
    end else if (ce) begin
        q <= d;
    end
end

endmodule

It synthesizes to:

What is going on? Why would adding CE to the sensitivity list make this synthesize to a buffer?

Thanks!

[steven_bellock · Accepted solution]

This is one of those cases where Vivado should be giving a synthesis error. Instead it synthesizes without issue, even though it can't implement the desired logic.

"Why would adding CE to the sensitivity list make this synthesize to a buffer?"

always @(posedge clk or posedge ce)

means that clr is synchronous to both clk and ce, which can't be done on an FPGA. Your first code example is the correct way to code a flip-flop with synchronous reset and enable.

[apetley]

Hi @vivadouser67 ,

I agree with @steven_bellock  Vivado should have issued error. This can't be modelled in flop. 

Btw, did you intend to put clr in senstitvity list

always@(posedge clk or posedge clr)

begin

 if(clr)

...

end

Thanks,

Ajay

[viviany]

First, adding CE in the sensitivity list is not a common way to describe an FF. This may be the reason why Vivado Synthesis gives the only-buffer result.

Second, please check the Synthesis log and see if it gives any message about this always statement. I would expect some messages in the log about this.

-vivian

[vivadouser67]

Your explanation makes perfect sense! It's sad to see the synthesis tool be so useless in this situation though. I'd say this is a bug. 

The only warning I see is: "[Synth 8-3331] design d_flip_flop has unconnected port ce" which is pointless.

Thank you!