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Visitor mnoone
Visitor
14,472 Views
Registered: ‎03-20-2013

Alternatives to parameter in Verilog?

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Hi - I've been using parameters above my module code in verilog files. This always generates a warning, but simulates just fine. However, this generates an error during synthesis. Is there an alternative that is acceptable?

 

I'm doing something along the lines of:

 

parameter num_bits = 8;
module foo(
input [num_bits - 1:0]
);

Thanks!!

 

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1 Solution

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Instructor
Instructor
18,822 Views
Registered: ‎08-14-2007

Re: Alternatives to parameter in Verilog?

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The parameter needs to be within the module declaration.  It should have been an

error for simulation as well.  In verilog 2001, you should place the parameter at the

top in the special parameter block like:

 

module foo

#(

  parameter param1 = 100,

  parameter param2 = 50

)

(

  input wire [param1-1:0] bar,

  output reg [parameter2-1:0] baz,

  output reg frob

);

 

For the older Verilog 95 method, you need to place the parameter between the module

port list and the port declarations like:

 

module foo (bar, baz, frob);

 

parameter param1 = 100;

parameter param2 = 50;

 

input [param1-1:0] bar;

output [param2-1:0] baz;

reg [param2-1:0] baz;

output frob;

reg frob;

 


I generally prefer the Verilog 2001 approach because everything is in one place.

-- Gabor
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9 Replies
Instructor
Instructor
18,823 Views
Registered: ‎08-14-2007

Re: Alternatives to parameter in Verilog?

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The parameter needs to be within the module declaration.  It should have been an

error for simulation as well.  In verilog 2001, you should place the parameter at the

top in the special parameter block like:

 

module foo

#(

  parameter param1 = 100,

  parameter param2 = 50

)

(

  input wire [param1-1:0] bar,

  output reg [parameter2-1:0] baz,

  output reg frob

);

 

For the older Verilog 95 method, you need to place the parameter between the module

port list and the port declarations like:

 

module foo (bar, baz, frob);

 

parameter param1 = 100;

parameter param2 = 50;

 

input [param1-1:0] bar;

output [param2-1:0] baz;

reg [param2-1:0] baz;

output frob;

reg frob;

 


I generally prefer the Verilog 2001 approach because everything is in one place.

-- Gabor
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Scholar austin
Scholar
14,467 Views
Registered: ‎02-27-2008

Re: Alternatives to parameter in Verilog?

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Scholar austin
Scholar
14,466 Views
Registered: ‎02-27-2008

Re: Alternatives to parameter in Verilog?

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Gabor,

 

Rather than just fix it for them, I supplied a nice reference paper....

 

But, I am sure they are happy you pointed out the problem (they should still erad that paper!).

Austin Lesea
Principal Engineer
Xilinx San Jose
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Instructor
Instructor
14,464 Views
Registered: ‎08-14-2007

Re: Alternatives to parameter in Verilog?

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Hi Austin,

 

  That's a good reference paper.  Any idea why the original code didn't generate

an error for Isim, when it had the parameter definition outside the module body?

I would think that illegal Verilog is illegal for all uses...

-- Gabor
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Instructor
Instructor
14,461 Views
Registered: ‎08-14-2007

Re: Alternatives to parameter in Verilog?

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Hmm, just noticed that the original thread had this same business and there was a warning

from Isim:

 

WARNING:HDLCompiler:1591 - "C:/HDL/tutorial1/SPI_Slave_R2.v" Line 29: Root scope declaration is not allowed in verilog 95/2K mode

 

In that case line 29 was the first place where the parameter "numbits" was used in within the module.

It would have made a lot more sense to refer to the line number of the parameter declaration...

-- Gabor
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Visitor mnoone
Visitor
14,440 Views
Registered: ‎03-20-2013

Re: Alternatives to parameter in Verilog?

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Gabor - thanks again for your continuing help. Your patience is appreciated :)

 

One thing that has been bothering me is that I don't know what Verilog version I should be trying to comply with... I'm using ISE and I'd assume that there's a flag somewhere to choose which version of Verilog to build to, but I simply can't find it! Any pointers?

 

Google suggests that somewhere there should be a checkbox for 2001, but I haven't been able to track it down. Does it make sense to code for 2001? (ie do most tools support it?) I made the mistake when I started coding C that I would use various things that were supported only in C99. Later on I discovered that most tools didn't support it (only C89) so I don't want to make that mistake again :)

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Instructor
Instructor
14,435 Views
Registered: ‎08-14-2007

Re: Alternatives to parameter in Verilog?

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XST supports Verilog 2001 since about version 8.1 if memory serves me correctly.  Almost

any modern synthesis tool should support Verilog 2001 by now.  In ISE, when you use the

GUI, you can right click on "Synthesize - XST" in the design pane to bring up a context menu,

and then select "process properties..."

 

The dialog box that pops up shows the settings.  At the bottom there is a drop-down

menu labeled "Property display level" which you should set to "Advanced" in order

to see all of the possible options.

 

For newer versions of XST, Verilog 2001 is supported by default and I don't think there's

any way to adjust that, since there are very few backward compatibility issues.  Even

in the versions where Verilog 2001 is an option, I believe that this option is selected by default.

 

I've noticed that most of the newer design files from Xilinx use the Verilog 2001 syntax for

module port declarations, but you'll probably find some that still don't because there was

no other reason to update the code.  In general the features of Verilog 2001 do not prevent you

from mixing in the older syntax in the same design.

 

I have changed all of my coding style to use Verilog 2001, because I find that it helps me

to keep everything related to a particular signal in one declaration, rather than spread out

over a number of lines which may not be close to eachother.  Some other rules that

help to reduce errors are:

 

1) Don't use positional port mapping unless there is no named port (i.e. only use

it for built-in gates).  Since the use of Verilog built-in gates is typically not done for

FPGA design, you should probably never need to use positional port mapping.

 

i.e.

 

some_module_name my_instance

(

  .data_out (foo),

  .data_in  (bar),

  .clk      (baz)

);

 

NOT:

 

some_module_name my_instance (foo, bar, baz);

 

2) Place "`default_nettype none" at the top of every file and "`default_nettype wire" at the

end of each file, and only include one module per file.  This prevents unintentional

implicit declaration of new nets when you mis-spell a signal name.  Note that using this

also means you must declare wires explicity even for input ports like:

 

  input wire [3:0] data_in,

 

instead of:

 

  input [3:0] data_in,

 

There's probably a lot more along this line, but those are helpful starters for Verilog 2001.

I keep a copy of the Doulos "Verilog Golden Reference Guide" on my desk and when I

need to look anything up I always look through their examples and "gotchas."

-- Gabor
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Newbie exam123
Newbie
14,387 Views
Registered: ‎03-30-2013

Re: Alternatives to parameter in Verilog?

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I've been working on my final year project which is based on hardware implementation of Image Encryption and I am finding a problem dealing with the matrix of the image. I have tried few ways, but the problem still persists.

 
The problem is:
I have an image (256 level -gray scale) stored in a 1-D Array (as 2-D array is not supported in I-VERILOG). I need to take some particular pixels in a particular order, for example:
@(posedge clk)
begin
M1<=Image[24*k+7:24*k];
M2<=Image[24*k+15:24*k+8];
M3<=Image[24*k+23:24*k+16];
end

where k and M1,M2,M3 are register data-type,and k is increasing at every clock pulse.(counter)
But on compiling, one of the errors is as shown :
Part select expressions must be constant.
This msb expression violates the rule: (('sd24)*(k))+('sd23)

The other error messages are similar. I even tried for loop for the same. But the same error persists.
What can be the other way to select a particular range of elements of an array and give it to a register? It will be really grateful if you can help me about the same.
 
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Historian
Historian
14,383 Views
Registered: ‎01-23-2009

Re: Alternatives to parameter in Verilog?

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First you should start a new topic for a new problem - not piggyback it on another topic.

 

As for your question - a new syntax was introduced in Verilog 2001 specifically for this situation, called the Variable part select.

 

In Verilog, everything must have a constant size. Using a part select with a variable, the tools cannot always determine that the span of the part select is a constant number of bits, so it doesn't try and rejects anything with a variable in the part select. However, what you are trying to do should be possible since all your part selects are, in fact, constant lengths. That's what the variable part select is for. Instead of stating the "first" and "last" bit you want, you either specify the first or the last, and the number of bits you want. The syntax "x[a +: b]" means "starting at a and going up by b bits"; x[ a-: b] means "starting at a and going down by b bits" - you can use either on any vector, regardless if it is declared with the larger number on the left or right (so this will work on "reg [79:0] x;" as well as "reg [0:79] x").

 

So for your operation you would use 

 

always @(posedge clk)
begin
   M1<=Image[24*k        +: 8];
   M2<=Image[24*k+8   +: 8];
   M3<=Image[24*k+16 +: 8];

end

 

Avrum