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Explorer
Explorer
824 Views
Registered: ‎11-01-2015

An issue about "use_dsp" with its value "logic"

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Hi All,

 

In ug901, it shows messages about use_dsp like below.

Accepted values are: “logic”, “yes”, and “no”:
• The “logic” value is used specifically for XOR structures to go into the DSP
primitives. For “logic”, this attribute can be placed on the module/architecture level
only.

 

I write a VHDL module like below.

 

library ieee;
use ieee.std_logic_1164.all;

entity dsp_logic is
generic (
W : positive := 16
);
port (
clk : in std_logic;
ain : in std_logic_vector(W-1 downto 0);
bin : in std_logic_vector(W-1 downto 0);
pout : out std_logic_vector(W-1 downto 0)
);
end dsp_logic;

architecture archi of dsp_logic is
attribute use_dsp : string;
attribute use_dsp of archi : architecture is "logic";
signal ain_r : std_logic_vector(W-1 downto 0) := (others => '0');
signal bin_r : std_logic_vector(W-1 downto 0) := (others => '0');
begin
process(clk)
begin
if rising_edge(clk) then
ain_r <= ain;
bin_r <= bin;
pout <= ain_r xor bin_r;
end if;
end process;
end archi;

 

But actually, it does not work. Could someone give a clue?

 

Thanks.

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1 Solution

Accepted Solutions
Voyager
Voyager
1,125 Views
Registered: ‎06-20-2017

Re: An issue about "use_dsp" with its value "logic"

Jump to solution

It looks like UG901 needs to be updated on a couple of fronts.  First, I could only get it to work with this:

  signal p_r  : std_logic_vector(oP'range)  := (others => '0');

  attribute use_dsp48        : string;
  attribute use_dsp48 of p_r : signal is "logic";

which contradicts UG901.  UG901 incorrectly states: 

The “logic” value is used specifically for XOR structures to go into the DSP
primitives. For “logic”, this attribute can be placed on the module/architecture level only. 

 

Note that the UG912 states more restrictions than I could find in UG901:

 

 

• LOGIC: For UltraScale architecture only. Use the DSP blocks to implement large/wide XOR functions.

This is also wrong, because I got it to work in a Kintex 7S device.  See solution below.

 

Lastly, my solution does not work for XOR bit widths less than or equal to 35.  Only bit widths greater than or equal to 36 worked for me.  My search was not exhaustive for widths or 7S v. US/US+. 

 

Toward helping Xilinx engineers better characterize the use_dsp attribute:

1. This did not work:

  attribute use_dsp48        : string;
  attribute use_dsp48 of rtl : architecture is "logic";

2.  This did work, in contradiction to UG901, but only for specific bit widths

  attribute use_dsp48        : string;
  attribute use_dsp48 of p_r : signal is "logic";

Hopefully somebody from Xilinx will be able to chime in here, and report that the documentation is being updated.

 

Here are a couple of test cases for the xilinx engineers, as well as others who might want to reverse engineer the attribute:

 

library ieee;
use ieee.std_logic_1164.all;

entity top is
generic (
  G_TW : positive := 36 -- 36 and 48 worked for me...35 and selected lower values did not
);
port (
  iCLK  : IN  std_logic;
  iA    : IN  std_logic_vector(G_TW-1 downto 0);
  iB    : IN  std_logic_vector(G_TW-1 downto 0);
  oP    : OUT std_logic_vector(G_TW-1 downto 0)
);
end top;

architecture RTL of top is

begin


dsp_logic_u1 : entity work.dsp_logic
generic map(
  G_W => iA'length
)
port map(
  iCLK => iCLK, 
  iA   => iA, 
  iB   => iB, 
  oP   => oP   
);


end RTL;

 

library ieee;
use ieee.std_logic_1164.all;

entity dsp_logic is
generic (
  G_W : positive := 48
);
port (
  iCLK  : IN  std_logic;
  iA    : IN  std_logic_vector(G_W-1 downto 0);
  iB    : IN  std_logic_vector(G_W-1 downto 0);
  oP    : OUT std_logic_vector(G_W-1 downto 0)
);
end dsp_logic;

architecture RTL of dsp_logic is

  signal a_r : std_logic_vector(iA'range)  := (others => '0');
  signal b_r : std_logic_vector(iB'range)  := (others => '0');
  signal p_r : std_logic_vector(oP'range)  := (others => '0');

  attribute use_dsp48        : string;
  attribute use_dsp48 of p_r : signal is "logic";
begin

  process(iCLK)
  begin
    if rising_edge(iCLK) then
      a_r <= iA;
      b_r <= iB;
      p_r <= a_r xor b_r;
    end if;
  end process;
  
  oP <= p_r;

end RTL;

Good luck everybody!

 

 

Adaptable Processing coming to an IP address near you.
3 Replies
Voyager
Voyager
1,126 Views
Registered: ‎06-20-2017

Re: An issue about "use_dsp" with its value "logic"

Jump to solution

It looks like UG901 needs to be updated on a couple of fronts.  First, I could only get it to work with this:

  signal p_r  : std_logic_vector(oP'range)  := (others => '0');

  attribute use_dsp48        : string;
  attribute use_dsp48 of p_r : signal is "logic";

which contradicts UG901.  UG901 incorrectly states: 

The “logic” value is used specifically for XOR structures to go into the DSP
primitives. For “logic”, this attribute can be placed on the module/architecture level only. 

 

Note that the UG912 states more restrictions than I could find in UG901:

 

 

• LOGIC: For UltraScale architecture only. Use the DSP blocks to implement large/wide XOR functions.

This is also wrong, because I got it to work in a Kintex 7S device.  See solution below.

 

Lastly, my solution does not work for XOR bit widths less than or equal to 35.  Only bit widths greater than or equal to 36 worked for me.  My search was not exhaustive for widths or 7S v. US/US+. 

 

Toward helping Xilinx engineers better characterize the use_dsp attribute:

1. This did not work:

  attribute use_dsp48        : string;
  attribute use_dsp48 of rtl : architecture is "logic";

2.  This did work, in contradiction to UG901, but only for specific bit widths

  attribute use_dsp48        : string;
  attribute use_dsp48 of p_r : signal is "logic";

Hopefully somebody from Xilinx will be able to chime in here, and report that the documentation is being updated.

 

Here are a couple of test cases for the xilinx engineers, as well as others who might want to reverse engineer the attribute:

 

library ieee;
use ieee.std_logic_1164.all;

entity top is
generic (
  G_TW : positive := 36 -- 36 and 48 worked for me...35 and selected lower values did not
);
port (
  iCLK  : IN  std_logic;
  iA    : IN  std_logic_vector(G_TW-1 downto 0);
  iB    : IN  std_logic_vector(G_TW-1 downto 0);
  oP    : OUT std_logic_vector(G_TW-1 downto 0)
);
end top;

architecture RTL of top is

begin


dsp_logic_u1 : entity work.dsp_logic
generic map(
  G_W => iA'length
)
port map(
  iCLK => iCLK, 
  iA   => iA, 
  iB   => iB, 
  oP   => oP   
);


end RTL;

 

library ieee;
use ieee.std_logic_1164.all;

entity dsp_logic is
generic (
  G_W : positive := 48
);
port (
  iCLK  : IN  std_logic;
  iA    : IN  std_logic_vector(G_W-1 downto 0);
  iB    : IN  std_logic_vector(G_W-1 downto 0);
  oP    : OUT std_logic_vector(G_W-1 downto 0)
);
end dsp_logic;

architecture RTL of dsp_logic is

  signal a_r : std_logic_vector(iA'range)  := (others => '0');
  signal b_r : std_logic_vector(iB'range)  := (others => '0');
  signal p_r : std_logic_vector(oP'range)  := (others => '0');

  attribute use_dsp48        : string;
  attribute use_dsp48 of p_r : signal is "logic";
begin

  process(iCLK)
  begin
    if rising_edge(iCLK) then
      a_r <= iA;
      b_r <= iB;
      p_r <= a_r xor b_r;
    end if;
  end process;
  
  oP <= p_r;

end RTL;

Good luck everybody!

 

 

Adaptable Processing coming to an IP address near you.
Explorer
Explorer
678 Views
Registered: ‎11-01-2015

Re: An issue about "use_dsp" with its value "logic"

Jump to solution

Hi @maps-mpls 

Thank you very much!

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Voyager
Voyager
654 Views
Registered: ‎06-20-2017

Re: An issue about "use_dsp" with its value "logic"

Jump to solution

You are welcome @araongao2015, I'm glad I could help.

Adaptable Processing coming to an IP address near you.
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