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Explorer
Explorer
781 Views
Registered: ‎12-12-2018

Array of interface in Systemverilog

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Hi,Everyone, I found that vivado can support about array of interface in vivado 19.2.


array of interface.png

So I wrote a piece of code to test this feature.

module apb3_m_test
#(
	parameter IF_ARRAY  = 2,
	parameter SIM 		= "FALSE",
	parameter DEBUG		= "FALSE"
)
(
	//------------------------------------------------
	// Port define
	//------------------------------------------------
	apb3.m			m_apb	[IF_ARRAY - 1 : 0],
	apb3.s			s_apb
);
	
	localparam DATA_WIDTH = s_apb.DATA_WIDTH;
	localparam ADDR_WIDTH = s_apb.ADDR_WIDTH;
	
	always_ff@(posedge s_apb.clk) begin
		m_apb[0].addr 		<= s_apb.addr;
		m_apb[0].enable		<= s_apb.enable;
		m_apb[0].sel		<= s_apb.sel;
		m_apb[0].wdata		<= s_apb.wdata;
		m_apb[0].write		<= s_apb.write;	
		m_apb[1].addr 		<= s_apb.addr;
		m_apb[1].enable		<= s_apb.enable;
		m_apb[1].sel		<= s_apb.sel;
		m_apb[1].wdata		<= s_apb.wdata;
		m_apb[1].write		<= s_apb.write;	
		s_apb.rdata			<= m_apb[0].rdata | m_apb[1].rdata;
		s_apb.ready			<= m_apb[0].ready | m_apb[1].ready;
		s_apb.slverr		<= m_apb[0].slverr | m_apb[1].slverr;
	end

endmodule

In this code apb.m and apb.s has define in other file. Vivado has return as below,

error.png

The problem is here. Array of Interface feature is not supported.

apb3.m			m_apb	[IF_ARRAY - 1 : 0],

If you modify the code to the following form,It can be systhesised

apb3.m			m_apb,

Does Vivado 19.2 support array of interface?

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Xilinx Employee
Xilinx Employee
744 Views
Registered: ‎07-21-2014

Hi @xumoxiao 

 

Array of interface is supported in Vivado 2019.2.

I have created a small test-case as per your description which vivado synthesis passes without any error. Can you please add your suggestions/modifications to reproduce this issue at my end?

interface intf1 (input i1 ,
       		input i2 ,
		output logic o1 );

	modport m1 (input i1, i2, output o1);
	
endinterface

module top (
	input clk,
	input i1[2:0],
	input i2[2:0],
	output o1 [2:0]);

	intf1 if_1 [3](i1, i2, o1);


	sub inst (clk, if_1.m1, if_1.m1);

endmodule

module sub (
	input clk,
	intf1.m1 m_1 [3],
	intf1.m1 m_2 [3]);

	always_ff@(posedge clk)
	begin
		m_1[0].o1 = m_2[0].i1 | m_2[0].i2;
	end

endmodule

 

-Shreyas

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4 Replies
Highlighted
Xilinx Employee
Xilinx Employee
745 Views
Registered: ‎07-21-2014

Hi @xumoxiao 

 

Array of interface is supported in Vivado 2019.2.

I have created a small test-case as per your description which vivado synthesis passes without any error. Can you please add your suggestions/modifications to reproduce this issue at my end?

interface intf1 (input i1 ,
       		input i2 ,
		output logic o1 );

	modport m1 (input i1, i2, output o1);
	
endinterface

module top (
	input clk,
	input i1[2:0],
	input i2[2:0],
	output o1 [2:0]);

	intf1 if_1 [3](i1, i2, o1);


	sub inst (clk, if_1.m1, if_1.m1);

endmodule

module sub (
	input clk,
	intf1.m1 m_1 [3],
	intf1.m1 m_2 [3]);

	always_ff@(posedge clk)
	begin
		m_1[0].o1 = m_2[0].i1 | m_2[0].i2;
	end

endmodule

 

-Shreyas

----------------------------------------------------------------------------------------------
Try to search answer for your issue in forums or xilinx user guides before you post a new thread.

Kindly note- Please mark the Answer as "Accept as solution" if information provided solves your query.
Give Kudos (star provided in right) to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

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Highlighted
Scholar
Scholar
715 Views
Registered: ‎09-16-2009

Which is line 30 in your code?

We've used SystemVerilog array of interfaces for quite a long time in Vivado - I'm thinking at least starting in 2017.4.  So I know it works.  There were a few more esoteric issues with Vivado early on (which could be work with), but as far as I'm aware everything's fine in the most recent realeases. 

I can't spot the exact trouble from inspection looking at your code.  Can you attach a more complete example to replicate the problem?

Regards,

Mark

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Scholar
Scholar
709 Views
Registered: ‎09-16-2009

I think your error has nothing to do with SystemVerilog arrays of interfaces.  I think your trouble is in these lines:

 

localparam DATA_WIDTH = s_apb.DATA_WIDTH;
localparam ADDR_WIDTH = s_apb.ADDR_WIDTH;

This sort of thing is only recently supported in Vivado. There's restrictions here that I'm totally clear on what Vivado accepts.  Try your example again, but instead have these parameters passed down into module "apb3_m_test" as actual parameters of the module.  Yes, it's not as clean, but start there to confirm that this is the problem.

Regards,

Mark

 

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Explorer
Explorer
653 Views
Registered: ‎12-12-2018

You are right, there is a problem with my upper code, thank you for your reply.

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