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mohamad
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Registered: ‎04-12-2021

Assignment under multiple single edges is not supported for synthesis

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Hello every body

I want to make a shift register in simulator ISE but when I writing the following code i get tht "Assignment under multiple single edges is not supported for synthesis" error

any answer i will appreciate that 

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bruce_karaffa
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Registered: ‎06-21-2017

Are you trying to assign a value to a signal on both teh rising edge and falling edge of a clock?  You cannot do this.  There are no DDR registers in the FPGA fabric, only on the output tiles. 

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bruce_karaffa
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Registered: ‎06-21-2017

Are you trying to assign a value to a signal on both teh rising edge and falling edge of a clock?  You cannot do this.  There are no DDR registers in the FPGA fabric, only on the output tiles. 

View solution in original post

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