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Visitor david_pavid
Visitor
5,670 Views
Registered: ‎03-12-2012

Asynchronous logic as delay lines: error in synthesize module, (synthesis attribute KEEP is "true")

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Hi everybody!

My experiments with asynchronous logic on FPGAs involve Verilog code that is not so common in usual FPGA applications.

I tried to implement a line of Buffer gates to serve as a delay line but it was not possible. I got these errors in the "Synthesize - XST" Process:

"

WARNING:Xst:638 - in unit switch Conflict on KEEP property on signal net<0> and net<1> net<1> signal will be lost.
WARNING:Xst:638 - in unit switch Conflict on KEEP property on signal net<0> and net<2> net<2> signal will be lost.
WARNING:Xst:638 - in unit switch Conflict on KEEP property on signal net<0> and net<3> net<3> signal will be lost.
WARNING:Xst:387 - The KEEP property attached to the net <net<0>> may hinder timing optimization.
You may achieve better results by removing this property

"

 

In the design, the line of Buffers was not implemented :(

 

How can I implement a line of asynchronous buffers as a physical delay line?

 

The errors above came from the following Verilog module (working on Altera boards), which should produce a pulse by XORing an input signal with a delayed version of the input signal :

 

module pulse(
input SWITCHES,
output SMA_out
);
wire [3:0] net;
// synthesis attribute KEEP of net is "true"

 

assign SMA_out = net[3] ^ SWITCHES;

 

//delay line implementation

assign net[0] = SWITCHES;
assign net[1] = net[0];
assign net[2] = net[1];
assign net[3] = net[2];

endmodule

 

Thanks!

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Teacher eteam00
Teacher
6,706 Views
Registered: ‎07-21-2009

Re: Asynchronous logic as delay lines: error in synthesize module, (synthesis attribute KEEP is "true")

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Asynchronous designs are not supported by the Xilinx tools, which you likely already know.

 

There is another recent and active thread on a very similar subject, which you might find interesting.

 

Delay lines and inverter chains have been discussed in these forums in great detail over the last year or two.  You might want to search the forums, you should be able to turn up these related discussions.  Some likely search strings:

  • "delay line"
  • "delay chain"

 -- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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2 Replies
Teacher eteam00
Teacher
6,707 Views
Registered: ‎07-21-2009

Re: Asynchronous logic as delay lines: error in synthesize module, (synthesis attribute KEEP is "true")

Jump to solution

Asynchronous designs are not supported by the Xilinx tools, which you likely already know.

 

There is another recent and active thread on a very similar subject, which you might find interesting.

 

Delay lines and inverter chains have been discussed in these forums in great detail over the last year or two.  You might want to search the forums, you should be able to turn up these related discussions.  Some likely search strings:

  • "delay line"
  • "delay chain"

 -- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Visitor david_pavid
Visitor
5,626 Views
Registered: ‎03-12-2012

Re: Asynchronous logic as delay lines: error in synthesize module, (synthesis attribute KEEP is "true")

Jump to solution

Thanks!

With the other forum posts I could figure out how I get asynchronous designs running: 

  • the Synthesizer accepts inverter chains but not buffer chains
  • Every asynchronous gate needs a "& reset" from an external Key or something

 

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