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Explorer
Explorer
3,884 Views
Registered: ‎04-19-2016

Axi lite register default value assigning

Hello,

I constructed a custom ip with one Axi-Lite slave interface.I want to give some default values into some signals(say some registers). 

Then, I wrote a VHDL process as like below in the user logic part of custom Axi-Lite ip template.

If rising edge( S_Axi_Clk)
If S_Axi_Aresetn = '0'
Write Some default values into some signals
else
Write slave register values into some signals
end

 

So I want to give my default values into registers when Axi-Lite reset assert.  I am assuming the axi-lite will be reset,  when FPGA power up. 


Does my aproach is true to give some default values into signal? 

 

I read the my default values from another register in SDK. ups. They are not my default values. so I could not give default values. 

 

how can I solve this problem, any idea ?


Regards,

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3 Replies
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Observer
Observer
3,845 Views
Registered: ‎10-28-2013

Re: Axi lite register default value assigning

Hi. Maybe you do somthing wrong in case stament of access the registers. Can you show sdk code and you custom ip code?
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Moderator
Moderator
3,777 Views
Registered: ‎07-21-2014

Re: Axi lite register default value assigning

@doner_t

 

Can you show us the custom IP interface details and register values? It would be helpful if you can share the custom IP here.

 

Thanks,
Anusheel
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Explorer
Explorer
3,765 Views
Registered: ‎04-19-2016

Re: Axi lite register default value assigning

Hello, 

 

Firstly thank you. 

 

I open the SDK , with a hello world application, to see only register values of my custom ip. I am waiting to see some default values that I assigned in VHDL in registers. 

 

I have an AXI-Lite template generated from Vivado.

 

Basicly, I added below  process under the user logic part in Axi Lite template

 

process (S_AXI_ACLK, S_AXI_ARESETN) is

begin

if(rising_edge(S_AXI_ACLK)) then

 if S_AXI_RESETN = '0' then

    signal1 <= '1';    -- default value for signal1.

    signal2 <= '1'     -- default value for signal2

    signal3 <= '0'    -- default value for signal3

    ...

else

    signal1 <= slv_reg0(0);    -- write to this signal.

    signal2 <= slv_reg0(1)     -- write to this signal

    signal3 <= slv_reg0(2)     -- write to this signal

 

end if;

end if;

end process

 

I have a sub-modul here. signal1, signal2 and signal3 go through to this sub-modul as input.

 

entity sub_modul is

port(

     input1  :in std_logic;

     input2  :in std_logic;

     input3  :in std_logic;

     output1 : out std_logic;

     output2 : out std_logic;

     output3 : out std_logic;

 

end sub_modul;

 

architecture Behavioral of sub_modul is

begin

 

  process(input1)

    begin

       case input1 is

        when '1' => 

           output1 <= '0'

        when '0' =>

          output1 <= '1'

      end case;

end process;

 

process(input2)

    begin

       case input2 is

        when '1' => 

           output2 <= '0'

        when '0' =>

          output2 <= '1'

      end case;

end process;

 

 

process(input3)

    begin

       case input3 is

        when '1' => 

           output3 <= '0'

        when '0' =>

          output3 <= '1'

      end case;

end process;

 

end Behavioral ;

 

And then this sub-modul gives 3 output. I can read the these three outputs from another axi-lite register.(say slv_reg1). Such as output1 value into slv_reg1(0),   output2 value into slv_reg1(1), output3 value into slv_reg1(2). 

 

When FPGA  power-up and then, I run the hello application basicly, immediately look at the my read register(slv_reg1).

I am waiting to see 001 in slv_reg1(in hex 0x00000001) in SDK memory, because of my default values correspondg to this value in the sub-modul.

 

But I saw the 111 in slv_reg1 (in hex 0x00000007) in SDK memory. Ups. My default value assigning did not work. I could see from this result signal1, signal2, signal3 started with logic '0' when FPGA power-up, without my default values. Problem is here. 

 

I can change the slv_reg1 values with entering some values into slv_reg0 in SDK. It is OK. I works correctly.

But I need also some correct default values in slv_reg1 when FPGA power-up.

 

Best regards,

 

 

 

 

 

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