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Registered: ‎05-07-2018

[BD 41-758] The following clock pins are not connected to a valid clock source

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I have a a portion of a Block Design I would like to use in a hierarchical BD design.  However, Vivado doesn't seem to like the clocks that simply go to IO ports.  All I want to do is generate OOC block design outputs and instantiate in the higher level BD of another design.  Can Vivado handle this?

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Registered: ‎05-07-2018

Re: [BD 41-758] The following clock pins are not connected to a valid clock source

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Thanks for the detailed response.  It turned out that having mismatched AXI clock/domain configuration parameters led to this error.  After fixing those, I was able to generate a wrapper and package my BD for instantiation into a BD of another design.  It appears that packaging is the *only* supported method of BD instantiation.  This is described well in UG994 v2018.3, but it wasn't clear if other methods would work.  Apparently not :)

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Registered: ‎01-22-2015

Re: [BD 41-758] The following clock pins are not connected to a valid clock source

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@corydearing 

In your lower-level block, you should be able to send the clock directly to a port of the block.  However, in the top-level block of your design (ie. the block that connects directly to the FPGA pins), you should not send the clock directly to a port.  Instead, you should use the ODDR component as described in Fig 2-18 or 2-19 of UG903 (v2019.1).  See also "Creating an Output Clock" on page 137 of UG949 (v2019.1).

Sending a clock directly to pin of the FPGA is called "pulling a clock from the clock tree" - and is considered bad practice.  In general, clocks should only be connected to the clock-pin of components (as we are doing with the ODDR), to clock-buffers (eg. BUFG), and to clock management tiles (eg. MMCM or PLL).

Mark

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Registered: ‎05-07-2018

Re: [BD 41-758] The following clock pins are not connected to a valid clock source

Jump to solution

Thanks for the detailed response.  It turned out that having mismatched AXI clock/domain configuration parameters led to this error.  After fixing those, I was able to generate a wrapper and package my BD for instantiation into a BD of another design.  It appears that packaging is the *only* supported method of BD instantiation.  This is described well in UG994 v2018.3, but it wasn't clear if other methods would work.  Apparently not :)

View solution in original post

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