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BIg overhead of Fifo

Highlighted
Visitor
Posts: 7
Registered: ‎08-08-2017

BIg overhead of Fifo

Hi everyone

 

I come from a software background so maybe I'm missing something, someone please please help. So I'm writing a debug trace funnel device, basically it takes 32 inputs every clock cycle, try to store them all in a fifo in one clock cycle (because new data will come in next cycle. Meanwhile, the number of valid input is different every time, so each clock cycle there maybe 0 to 32 inputs that need to be stored). For the output, the fifo output them one by one in order.

So I wrote it and successfully synthesized it, the component works just fine, but the overhead, is SCARY HUGE. I don't understand how a simple fifo of 6 slots can be this big. Can someone please help? I attached the fifo file and some relative record definition.


library IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; use work.defs.all; entity fifo32 is Generic ( constant FIFO_DEPTH : positive := 8 ); Port ( CLK : in STD_LOGIC; RST : in STD_LOGIC; --WriteEn : in STD_LOGIC; --DataVal: in ALL_T; --DataLen: in std_logic_vector(4 downto 0); DataIn : in ALL_T; --ReadEn : in STD_LOGIC; DataOut : out TST_TO; Full : out STD_LOGIC := '0' ); end fifo32; architecture rtl of fifo32 is --signal td1: std_logic_vector(31 downto 0); --signal td2: std_logic_vector(31 downto 0); begin -- Memory Pointer Process fifo_proc : process (clk) type FIFO_Memory is array (0 to FIFO_DEPTH - 1) of TST_TO; variable Memory : FIFO_Memory; variable Head : natural range 0 to FIFO_DEPTH - 1; variable Tail : natural range 0 to FIFO_DEPTH - 1; variable Looped : boolean; variable len: integer :=0; variable i: integer :=0; variable first: boolean := true; variable amount: integer :=0; begin if rising_edge(CLK) then if RST = '1' then Head := 0; Tail := 0; Looped := false; Full <= '0'; -- Empty <= '1'; DataOut.val<= '0'; else first := true; i := 0; -- if (WriteEn = '1') then while (i<32) loop if (((Looped = false) or (Head /= Tail))) and DataIn(i).val='1' then if (first=true) then Memory(Head) := (DataIn(i).val,DataIn(i).sender,DataIn(i).receiver,DataIn(i).cmd,DataIn(i).tag,DataIn(i).id,DataIn(i).adr,'1') ; first := false; else Memory(Head) := (DataIn(i).val,DataIn(i).sender,DataIn(i).receiver,DataIn(i).cmd,DataIn(i).tag,DataIn(i).id,DataIn(i).adr,'0') ; end if; -- Increment Head pointer as needed if (Head = FIFO_DEPTH - 1) then Head := 0; Looped := true; else Head := Head + 1; end if; end if; i := i+1; amount := amount +1; if (Head = Tail) then if Looped then Full <= '1'; report "the fifo is too small, it is full!!!!!!!!!!!!"; else DataOut.val<='0'; end if; else Full <= '0'; end if; end loop; if ((Looped = true) or (Head /= Tail)) then -- Update data output DataOut <= Memory(Tail); amount := amount -1; -- Update Tail pointer as needed if (Tail = FIFO_DEPTH - 1) then Tail := 0; Looped := false; else Tail := Tail + 1; end if; end if; end if; end if; end process; end rtl;
library ieee;
use ieee.std_logic_1164.all;

package defs is
  constant MSG_WIDTH : positive := 73;
  constant WMSG_WIDTH : positive := 76;
  constant BMSG_WIDTH : positive := 553;
  
  constant CMD_WIDTH : positive := 8;
  constant ADR_WIDTH : positive := 32;
  constant DAT_WIDTH : positive := 32;
  constant IP_CT: positive := 4;
 subtype IP_VECT_T is std_logic_vector(11 downto 0);
   type IP_T is (CPU0, CPU1, CACHE0, CACHE1,
                 SA, MEM, GFX, PMU,
                 AUDIO, USB, UART,
                 NONE);
   type STATE is (one, two, three, four, five, six);
   type IP_VECT_ARRAY_T is array(IP_T) of IP_VECT_T;
   constant ip_enc : IP_VECT_ARRAY_T := (x"001", x"002", x"004", x"008",
                                         x"010", x"020", x"040", x"080",
                                         x"100", x"200", x"400",
                                         x"000");
  type MSG_T is record
   val       : std_logic;                     -- valid bit;
   cmd       : std_logic_vector(7 downto 0);
   tag       : std_logic_vector(7 downto 0);  -- src
   id        : std_logic_vector(7 downto 0);  --sequence id
   adr       : std_logic_vector(31 downto 0);
   dat       : std_logic_vector(31 downto 0);
end record MSG_T;

type TST_T is record
   val       : std_logic;                     -- valid bit;
   sender : IP_T;
   receiver: IP_T;
   cmd       : std_logic_vector(7 downto 0);
   tag       : std_logic_vector(7 downto 0);  -- src
   id        : std_logic_vector(7 downto 0);  --sequence id
   adr       : std_logic_vector(1 downto 0);
end record TST_T;

type AXI_T is record
   val       : std_logic;                     -- valid bit;
   sender : IP_T;
   receiver: IP_T;
   cmd       : std_logic;
   tag       : std_logic_vector(7 downto 0);  -- src
   id        : std_logic_vector(7 downto 0);  --sequence id
   adr       : std_logic_vector(1 downto 0);
end record TST_T;

type cacheline is record
	val       : std_logic;                     -- valid bit;
   cmd       : std_logic_vector(7 downto 0);
   tag       : std_logic_vector(7 downto 0);  -- src
   id        : std_logic_vector(7 downto 0);  --sequence id
   adr       : std_logic_vector(31 downto 0);
   dat       : std_logic_vector(511 downto 0);
   frontinfo : std_logic_vector(35 downto 0);
end record cacheline;

  type BMSG_T is record
   val       : std_logic;                     -- valid bit;
   cmd       : std_logic_vector(7 downto 0);
   tag       : std_logic_vector(7 downto 0);  -- src
   id        : std_logic_vector(7 downto 0);  --sequence id
   adr       : std_logic_vector(31 downto 0);
   dat       : std_logic_vector(511 downto 0);
  end record BMSG_T;

  type SNP_RES_T is record
    hit     : std_logic;
    msg     : MSG_T;
  end record SNP_RES_T;
  
  constant ZERO_MSG : MSG_T := ('0',
                                (others => '0'),
                                (others => '0'),
                                (others => '0'),
                                (others => '0'),
                                (others => '0'));

  constant ZERO_BMSG : BMSG_T := ('0',
                                  (others => '0'),
                                  (others => '0'),
                                  (others => '0'),
                                  (others => '0'),
                                  (others => '0'));
constant ZERO_c : cacheline := ('0',
                                                                    (others => '0'),
                                                                    (others => '0'),
                                                                    (others => '0'),
                                                                    (others => '0'),
                                                                    (others => '0'),
                                                                    (others => '0'));
  
--  subtype MSG_T is std_logic_vector(MSG_WIDTH-1 downto 0);
  subtype CMD_T is std_logic_vector(CMD_WIDTH-1 downto 0);
  subtype ADR_T is std_logic_vector(ADR_WIDTH-1 downto 0);
  subtype DAT_T is std_logic_vector(DAT_WIDTH-1 downto 0);

--  subtype WMSG_T is std_logic_vector(WMSG_WIDTH-1 downto 0);
--  subtype BMSG_T is std_logic_vector(BMSG_WIDTH-1 downto 0); -- bus message
  subtype DEST_T is std_logic_vector(2 downto 0);

--  constant ZERO_MSG : MSG_T := (others => '0');
--  constant ZERO_BMSG : BMSG_T := (others => '0');
  
  
  constant READ_CMD  : CMD_T := "01000000"; --x"40";
  constant WRITE_CMD : CMD_T := "10000000"; --x"80";
  constant PWRUP_CMD : CMD_T := "00100000"; --x"20";
  constant PWRDN_CMD : CMD_T := "00010000"; --x"10";
  constant ZEROS_CMD : CMD_T := x"00";
  constant ONES_CMD : CMD_T  := x"ff";

  constant ZERO_480 : std_logic_vector(479 downto 0) := (others => '0');

  constant ZERO_TAG, ZERO_ID : std_logic_vector(7 downto 0) := x"00";
  constant ZEROS32, ZERO_ADR, ZERO_DAT : std_logic_vector(31 downto 0) := (others => '0');
  constant ONES32 : std_logic_vector(31 downto 0) := (others => '1');

  -- constant VAL_MASK : MSG_T := "1" & ZEROS_CMD & ZEROS32 & ZEROS32;
  -- constant CMD_MASK : MSG_T := "0" & ONES_CMD & ZEROS32 & ZEROS32;
  -- constant ADR_MASK : MSG_T := "0" & ZEROS_CMD & ONES32 & ZEROS32;
  -- constant DAT_MASK : MSG_T := "0" & ZEROS_CMD & ZEROS32 & ONES32;

  subtype IPTAG_T is std_logic_vector(7 downto 0);
  constant CPU0_TAG  : IPTAG_T := x"00";
  constant GFX_TAG   : IPTAG_T := x"01";
  constant UART_TAG  : IPTAG_T := x"02";
  constant USB_TAG   : IPTAG_T := x"03";
  constant AUDIO_TAG : IPTAG_T := x"04";
  constant CPU1_TAG  : IPTAG_T := x"05";
  -- TODO ips should b in order but b careful changing as it may break stg else!

 

  --constant TOMEM_ADR : ADR_T := x"80"; --1XXX...
  --constant TOGFX_ADR : ADR_T := x"00"; --X00X...
  --constant TOUART_ADR : ADR_T := x"20"; --X01X...
  --constant TOUSB_ADR : ADR_T := x"40"; --X10X...
  --constant TOAUDIO_ADR : ADR_T := x"60"; --X11X...  

  
  -- indices
  --constant MEM_FOUND_IDX : positive := 56;
  constant MSG_VAL_IDX : natural := 72;
  constant MSG_CMD_IDX : natural := 64;
  constant MSG_ADR_IDX : natural := 32;  
  constant MSG_DAT_IDX : natural := 0;

  -- PWRCMD is:
  --  a total of 73 bits:
  --     valid_bit & cmd[8] & src[8] & dst[8] & unused[24] 
  
end defs;

 

Visitor
Posts: 7
Registered: ‎08-08-2017

Re: BIg overhead of Fifo

The synthesis

#-----------------------------------------------------------
# Vivado v2017.2 (64-bit)
# SW Build 1909853 on Thu Jun 15 18:39:09 MDT 2017
# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017
# Start of session at: Mon Nov 13 16:51:36 2017
# Process ID: 6008
# Current directory: C:/Users/cao2/Desktop/soci/soci/soc_ic/soc_ic.runs/synth_4
# Command line: vivado.exe -log fifo32.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source fifo32.tcl
# Log file: C:/Users/cao2/Desktop/soci/soci/soc_ic/soc_ic.runs/synth_4/fifo32.vds
# Journal file: C:/Users/cao2/Desktop/soci/soci/soc_ic/soc_ic.runs/synth_4\vivado.jou
#-----------------------------------------------------------
source fifo32.tcl -notrace
Command: synth_design -top fifo32 -part xc7z020clg484-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg484'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg484'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 4604 
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 364.027 ; gain = 81.859
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'fifo32' [C:/Users/cao2/Desktop/soci/soci/soc_ic/soc_ic.srcs/sources_1/new/32fifo.vhd:24]
	Parameter FIFO_DEPTH bound to: 8 - type: integer 
WARNING: [Synth 8-6014] Unused sequential element first_reg was removed.  [C:/Users/cao2/Desktop/soci/soci/soc_ic/soc_ic.srcs/sources_1/new/32fifo.vhd:54]
WARNING: [Synth 8-6014] Unused sequential element i_reg was removed.  [C:/Users/cao2/Desktop/soci/soci/soc_ic/soc_ic.srcs/sources_1/new/32fifo.vhd:55]
WARNING: [Synth 8-6014] Unused sequential element len_reg was removed. 
INFO: [Synth 8-256] done synthesizing module 'fifo32' (1#1) [C:/Users/cao2/Desktop/soci/soci/soc_ic/soc_ic.srcs/sources_1/new/32fifo.vhd:24]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 489.273 ; gain = 207.105
---------------------------------------------------------------------------------

Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 489.273 ; gain = 207.105
---------------------------------------------------------------------------------
INFO: [Device 21-403] Loading part xc7z020clg484-1
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [C:/Users/cao2/Desktop/soci/soci/soc_ic/soc_ic.srcs/constrs_1/imports/zedboard_master_XDC_RevC_D_v3/zedboard_master_XDC_RevC_D_v3.xdc]
WARNING: [Vivado 12-584] No ports matched 'Clock'. [C:/Users/cao2/Desktop/soci/soci/soc_ic/soc_ic.srcs/constrs_1/imports/zedboard_master_XDC_RevC_D_v3/zedboard_master_XDC_RevC_D_v3.xdc:87]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/cao2/Desktop/soci/soci/soc_ic/soc_ic.srcs/constrs_1/imports/zedboard_master_XDC_RevC_D_v3/zedboard_master_XDC_RevC_D_v3.xdc:87]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'Clock'. [C:/Users/cao2/Desktop/soci/soci/soc_ic/soc_ic.srcs/constrs_1/imports/zedboard_master_XDC_RevC_D_v3/zedboard_master_XDC_RevC_D_v3.xdc:88]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/cao2/Desktop/soci/soci/soc_ic/soc_ic.srcs/constrs_1/imports/zedboard_master_XDC_RevC_D_v3/zedboard_master_XDC_RevC_D_v3.xdc:88]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'Clock'. [C:/Users/cao2/Desktop/soci/soci/soc_ic/soc_ic.srcs/constrs_1/imports/zedboard_master_XDC_RevC_D_v3/zedboard_master_XDC_RevC_D_v3.xdc:89]
CRITICAL WARNING: [Vivado 12-4739] create_clock:No valid object(s) found for '-objects [get_ports Clock]'. [C:/Users/cao2/Desktop/soci/soci/soc_ic/soc_ic.srcs/constrs_1/imports/zedboard_master_XDC_RevC_D_v3/zedboard_master_XDC_RevC_D_v3.xdc:89]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-584] No ports matched 'rx_in'. [C:/Users/cao2/Desktop/soci/soci/soc_ic/soc_ic.srcs/constrs_1/imports/zedboard_master_XDC_RevC_D_v3/zedboard_master_XDC_RevC_D_v3.xdc:92]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/cao2/Desktop/soci/soci/soc_ic/soc_ic.srcs/constrs_1/imports/zedboard_master_XDC_RevC_D_v3/zedboard_master_XDC_RevC_D_v3.xdc:92]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'rx_in'. [C:/Users/cao2/Desktop/soci/soci/soc_ic/soc_ic.srcs/constrs_1/imports/zedboard_master_XDC_RevC_D_v3/zedboard_master_XDC_RevC_D_v3.xdc:93]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/cao2/Desktop/soci/soci/soc_ic/soc_ic.srcs/constrs_1/imports/zedboard_master_XDC_RevC_D_v3/zedboard_master_XDC_RevC_D_v3.xdc:93]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'tx_out'. [C:/Users/cao2/Desktop/soci/soci/soc_ic/soc_ic.srcs/constrs_1/imports/zedboard_master_XDC_RevC_D_v3/zedboard_master_XDC_RevC_D_v3.xdc:96]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/cao2/Desktop/soci/soci/soc_ic/soc_ic.srcs/constrs_1/imports/zedboard_master_XDC_RevC_D_v3/zedboard_master_XDC_RevC_D_v3.xdc:96]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'tx_out'. [C:/Users/cao2/Desktop/soci/soci/soc_ic/soc_ic.srcs/constrs_1/imports/zedboard_master_XDC_RevC_D_v3/zedboard_master_XDC_RevC_D_v3.xdc:97]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/cao2/Desktop/soci/soci/soc_ic/soc_ic.srcs/constrs_1/imports/zedboard_master_XDC_RevC_D_v3/zedboard_master_XDC_RevC_D_v3.xdc:97]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'reset'. [C:/Users/cao2/Desktop/soci/soci/soc_ic/soc_ic.srcs/constrs_1/imports/zedboard_master_XDC_RevC_D_v3/zedboard_master_XDC_RevC_D_v3.xdc:219]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/cao2/Desktop/soci/soci/soc_ic/soc_ic.srcs/constrs_1/imports/zedboard_master_XDC_RevC_D_v3/zedboard_master_XDC_RevC_D_v3.xdc:219]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'reset'. [C:/Users/cao2/Desktop/soci/soci/soc_ic/soc_ic.srcs/constrs_1/imports/zedboard_master_XDC_RevC_D_v3/zedboard_master_XDC_RevC_D_v3.xdc:220]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/cao2/Desktop/soci/soci/soc_ic/soc_ic.srcs/constrs_1/imports/zedboard_master_XDC_RevC_D_v3/zedboard_master_XDC_RevC_D_v3.xdc:220]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [C:/Users/cao2/Desktop/soci/soci/soc_ic/soc_ic.srcs/constrs_1/imports/zedboard_master_XDC_RevC_D_v3/zedboard_master_XDC_RevC_D_v3.xdc]
Completed Processing XDC Constraints

INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 797.840 ; gain = 0.000
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 797.840 ; gain = 515.672
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7z020clg484-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 797.840 ; gain = 515.672
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 797.840 ; gain = 515.672
---------------------------------------------------------------------------------
INFO: [Synth 8-5544] ROM "Looped" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:33 ; elapsed = 00:00:34 . Memory (MB): peak = 797.840 ; gain = 515.672
---------------------------------------------------------------------------------

Report RTL Partitions: 
+------+--------------+------------+----------+
|      |RTL Partition |Replication |Instances |
+------+--------------+------------+----------+
|1     |fifo32__GB0   |           1|     44677|
|2     |fifo32__GB1   |           1|     21336|
|3     |fifo32__GB2   |           1|     42721|
+------+--------------+------------+----------+
---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      3 Bit       Adders := 33    
+---Registers : 
	                8 Bit    Registers := 27    
	                5 Bit    Registers := 18    
	                3 Bit    Registers := 1     
	                2 Bit    Registers := 9     
	                1 Bit    Registers := 20    
+---Muxes : 
	   2 Input      8 Bit        Muxes := 1536  
	   2 Input      5 Bit        Muxes := 1024  
	   2 Input      3 Bit        Muxes := 3313  
	   2 Input      2 Bit        Muxes := 512   
	   2 Input      1 Bit        Muxes := 1774  
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics 
---------------------------------------------------------------------------------
Hierarchical RTL Component report 
Module fifo32 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      3 Bit       Adders := 33    
+---Registers : 
	                8 Bit    Registers := 27    
	                5 Bit    Registers := 18    
	                3 Bit    Registers := 1     
	                2 Bit    Registers := 9     
	                1 Bit    Registers := 20    
+---Muxes : 
	   2 Input      8 Bit        Muxes := 1536  
	   2 Input      5 Bit        Muxes := 1024  
	   2 Input      3 Bit        Muxes := 3313  
	   2 Input      2 Bit        Muxes := 512   
	   2 Input      1 Bit        Muxes := 1774  
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 220 (col length:60)
BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:06 ; elapsed = 00:01:07 . Memory (MB): peak = 1262.918 ; gain = 980.750
---------------------------------------------------------------------------------

Report RTL Partitions: 
+------+--------------+------------+----------+
|      |RTL Partition |Replication |Instances |
+------+--------------+------------+----------+
|1     |fifo32__GB0   |           1|      5485|
|2     |fifo32__GB1   |           1|     11104|
|3     |fifo32__GB2   |           1|     10886|
+------+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:16 ; elapsed = 00:01:17 . Memory (MB): peak = 1262.918 ; gain = 980.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:01:16 ; elapsed = 00:01:17 . Memory (MB): peak = 1262.918 ; gain = 980.750
---------------------------------------------------------------------------------

Report RTL Partitions: 
+------+--------------+------------+----------+
|      |RTL Partition |Replication |Instances |
+------+--------------+------------+----------+
|1     |fifo32__GB0   |           1|      5485|
|2     |fifo32__GB1   |           1|     11104|
|3     |fifo32__GB2   |           1|     10886|
+------+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:01:19 ; elapsed = 00:01:20 . Memory (MB): peak = 1262.918 ; gain = 980.750
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
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Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
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Start Final Netlist Cleanup
---------------------------------------------------------------------------------
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Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
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Finished IO Insertion : Time (s): cpu = 00:01:20 ; elapsed = 00:01:22 . Memory (MB): peak = 1262.918 ; gain = 980.750
---------------------------------------------------------------------------------

Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
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Finished Renaming Generated Instances : Time (s): cpu = 00:01:20 ; elapsed = 00:01:22 . Memory (MB): peak = 1262.918 ; gain = 980.750
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
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Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:21 ; elapsed = 00:01:22 . Memory (MB): peak = 1262.918 ; gain = 980.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
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Finished Renaming Generated Ports : Time (s): cpu = 00:01:21 ; elapsed = 00:01:22 . Memory (MB): peak = 1262.918 ; gain = 980.750
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Start Handling Custom Attributes
---------------------------------------------------------------------------------
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Finished Handling Custom Attributes : Time (s): cpu = 00:01:21 ; elapsed = 00:01:22 . Memory (MB): peak = 1262.918 ; gain = 980.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:01:21 ; elapsed = 00:01:22 . Memory (MB): peak = 1262.918 ; gain = 980.750
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Start Writing Synthesis Report
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Report BlackBoxes: 
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage: 
+------+------+------+
|      |Cell  |Count |
+------+------+------+
|1     |BUFG  |     1|
|2     |LUT1  |     1|
|3     |LUT2  |   134|
|4     |LUT3  |   678|
|5     |LUT4  |   815|
|6     |LUT5  |  3010|
|7     |LUT6  |  4332|
|8     |MUXF7 |    24|
|9     |FDRE  |   355|
|10    |IBUF  |  1186|
|11    |OBUF  |    39|
+------+------+------+

Report Instance Areas: 
+------+---------+-------+------+
|      |Instance |Module |Cells |
+------+---------+-------+------+
|1     |top      |       | 10575|
+------+---------+-------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:01:21 ; elapsed = 00:01:22 . Memory (MB): peak = 1262.918 ; gain = 980.750
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:01:05 ; elapsed = 00:01:15 . Memory (MB): peak = 1262.918 ; gain = 672.184
Synthesis Optimization Complete : Time (s): cpu = 00:01:21 ; elapsed = 00:01:23 . Memory (MB): peak = 1262.918 ; gain = 980.750
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 1186 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
WARNING: [Netlist 29-101] Netlist 'fifo32' is not ideal for floorplanning, since the cellview 'fifo32' contains a large number of primitives.  Please consider enabling hierarchy in synthesis if you want to do floorplanning.
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

13 Infos, 13 Warnings, 9 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:01:25 ; elapsed = 00:01:26 . Memory (MB): peak = 1262.918 ; gain = 988.605
INFO: [Common 17-1381] The checkpoint 'C:/Users/cao2/Desktop/soci/soci/soc_ic/soc_ic.runs/synth_4/fifo32.dcp' has been generated.
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1262.918 ; gain = 0.000
INFO: [Common 17-206] Exiting Vivado at Mon Nov 13 16:53:08 2017...

report