Hello!
I have a problem with Vivado 2019.2 synthesis (behavioral simulation works as expected). I have a module instance array, where the ports are connected to arrays of their respective types, expecting each module instance to pick up the corresponding array element. This used to work fine, but recently I modified the type of one of the ports, which became a struct containing another struct. Simulation continued to work, but I get an error during synthesis.
Minimal example (System Verilog):
========
typedef struct {
logic c;
} B;
typedef struct {
B b;
//logic b;
} A;
module Mymodule(
input A a
);
endmodule
module Top(
);
A a;
Mymodule mymodule (
.a(a)
);
A aa[0:9];
Mymodule mymodules[0:9] (
.a(aa)
);
endmodule
========
synth_design gives me:
ERROR: [Synth 8-448] named port connection 'a[b[c]]' does not exist for instance 'mymodules' of module 'Mymodule' [xxx.sv:26]
Connecting a single (non-array) instance is fine. Replacing the "B b" definition with "logic b" to eliminate the struct-in-struct also works. Please confirm if this is a bug. Cheers.
