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Visitor nleclerc
Visitor
9,057 Views
Registered: ‎03-07-2016

BUG - Streaming concatenation in non-assignment context

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Hi,

 

  I found what I believe to be a bug in synthesis.  Using systemverilog streaming operator to reverse a vector.

 

The following constuct leads to an error: ([Synth 8-27] streaming concatenation in non-assignment context not supported)

 

assign d_w = REFLECT_INPUT?d:{<<{d}};

But if you break it in two:

assign dRev_w = {<<{d}};
assign d_w = REFLECT_INPUT?d:dRev_w;

works like a charm.

 

 

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Teacher muzaffer
Teacher
7,266 Views
Registered: ‎03-31-2012

Re: BUG - Streaming concatenation in non-assignment context

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IEEE Std 1800 says: "It shall be an error to use a streaming_concatenation as an operand in an expression without first casting it to a bit-stream type" so I think Vivado is doing the right thing complaining here.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

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1 Reply
Teacher muzaffer
Teacher
7,267 Views
Registered: ‎03-31-2012

Re: BUG - Streaming concatenation in non-assignment context

Jump to solution
IEEE Std 1800 says: "It shall be an error to use a streaming_concatenation as an operand in an expression without first casting it to a bit-stream type" so I think Vivado is doing the right thing complaining here.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

View solution in original post