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debugger
Observer
Observer
643 Views
Registered: ‎08-14-2015

Best way to instantiate a FF with a negative edge clocking in Vivado for K7 device

Hi,

I am working on a FPGA design that uses FFs to sample same data on both edges of a given clock. Which is the best way to use a negative edge FF?

1- by using FDRE_1 primitive which will use the clock inverter within the FF

2- by inverting the clock externally with a LUT resource before the FF.

Please let me know what do you think about it or which is the best, or if there is another option please let me know.

Many thanks,

Vlad

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4 Replies
dpaul24
Scholar
Scholar
636 Views
Registered: ‎08-07-2014

@debugger ,

To infer a flop that samples data either on the falling-edge or rising-edge, I never use primitives.

Just sample the data at the falling edge of the main clock. The tools will do the rest.

But if you want the same flop to sample data at both rising- and falling- edges, then use either an IDDR or ODDR as per your use case.

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debugger
Observer
Observer
611 Views
Registered: ‎08-14-2015

@dpaul24 Thank you for your answer. Indeed there is also an option to do as you suggest. I have another question, why Vivado keep adding an IDDR resource when I am trying to sample a signal with 2 different FFs with one configured to sample on rising and the other one on falling edges? There is a way to prevent that?

Thanks.

Vlad

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dpaul24
Scholar
Scholar
599 Views
Registered: ‎08-07-2014

@debugger ,

Should be. I do not have the answer in my mind.

Please check the synthesis guide documentation. It would be the UG901 for the Vivado version you are using.

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joancab
Teacher
Teacher
596 Views
Registered: ‎05-11-2015

If you want to sample some pin on the rising and falling edges of a clock that calls naturally for an IDDR, even if they are "independent processes". The processes may be, but the clocks aren't. Negating a clock with an LUT is not the same as triggering an FF with neg edge time-wise. Timing is different. 

If you need to sample at both edges, use IDDR and split the data. If you still want to carry on with independent FFs try generating two clocks phased out 180 deg, that's much better than inverters. i personally wouldn't waste an MMCM to do that, but...