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onkarkk1
Explorer
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Registered: ‎12-29-2008

Block RAM or Distributed RAM

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Hi,

 

I have a doubt regarding selection of RAM for perticular design , i.e., how to decide that it should be of block RAM or distributed RAM .

 

Another doubt is :::

 Using xst coding guide lines for block RAM i have written code ,if it is a small memory then it is inferring distributed RAM automatically and saying that some performance as reasons. Could anyone explain this ???

 

In the same lines my doubt continues .. suppose if i want it to be block ram itself in project navigator i have the option in sources window -->synthesis properties --> HDL options--> ram_style = block  ,    In the same way if i am operating from XPS window , if i am using small memory and i want it to be of type block RAM , how to do that ??

 

I have reffered documents like : design constraints guide of xilinx  but i did'nt exactly get an example where to place the constraint , though i have placed the constraint in UCF file (which is wrong i think), Please correct me and guide me. 

 

Thanks in advance,

regards,

Krishna Kishore 

 

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bassman59
Historian
Historian
36,674 Views
Registered: ‎02-25-2008

onkarkk1 wrote:

Hi,

 

I have a doubt regarding selection of RAM for perticular design , i.e., how to decide that it should be of block RAM or distributed RAM .

 


 

A reasonable rule of thumb: if you need a lot of RAM, you want to use BRAM, otherwise your FPGA resources will be eaten up implementing the RAM in LUTs.


Another doubt is :::

 Using xst coding guide lines for block RAM i have written code ,if it is a small memory then it is inferring distributed RAM automatically and saying that some performance as reasons. Could anyone explain this ???


LUT (distributed) RAM will be faster and less wasteful for "smal" memories. So the tools helpfully use distributed RAM if it is a better fit for your application. Usually, this is a good thing.

 


 

In the same lines my doubt continues .. suppose if i want it to be block ram itself in project navigator i have the option in sources window -->synthesis properties --> HDL options--> ram_style = block  ,    In the same way if i am operating from XPS window , if i am using small memory and i want it to be of type block RAM , how to do that ??

 


That's a very good question, and I really don't know!

 

-a

----------------------------Yes, I do this for a living.

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bassman59
Historian
Historian
36,675 Views
Registered: ‎02-25-2008

onkarkk1 wrote:

Hi,

 

I have a doubt regarding selection of RAM for perticular design , i.e., how to decide that it should be of block RAM or distributed RAM .

 


 

A reasonable rule of thumb: if you need a lot of RAM, you want to use BRAM, otherwise your FPGA resources will be eaten up implementing the RAM in LUTs.


Another doubt is :::

 Using xst coding guide lines for block RAM i have written code ,if it is a small memory then it is inferring distributed RAM automatically and saying that some performance as reasons. Could anyone explain this ???


LUT (distributed) RAM will be faster and less wasteful for "smal" memories. So the tools helpfully use distributed RAM if it is a better fit for your application. Usually, this is a good thing.

 


 

In the same lines my doubt continues .. suppose if i want it to be block ram itself in project navigator i have the option in sources window -->synthesis properties --> HDL options--> ram_style = block  ,    In the same way if i am operating from XPS window , if i am using small memory and i want it to be of type block RAM , how to do that ??

 


That's a very good question, and I really don't know!

 

-a

----------------------------Yes, I do this for a living.

View solution in original post

jprovidenza
Voyager
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27,985 Views
Registered: ‎08-30-2007

Several comments -

 

If you need async read, you need to use distributed ram.  Block ram is completely synchronous

for both reads and writes.

 

To force XST to use one style or the other, take a look at the RAM_STYLE synthesis attribute:

    http://www.xilinx.com/itp/xilinx7/books/data/docs/cgd/cgd0148_109.html

 

Hope this helps!

 

John Providenza

onkarkk1
Explorer
Explorer
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Registered: ‎12-29-2008

Thank you  Bassman and John,

I will go through that link , some how it seems i have gone through that link and some attributes regarding to synthesis while writing code but i could not solve the issue , may be i would have done some mistake i will go through once again and let you know.

 

Thanks again for your response,

 

regards,

Krishna Kishore 

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onkarkk1
Explorer
Explorer
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Registered: ‎12-29-2008

Hi,

 

I have worked through that link,  I want to make a correction as per my knowledge and results i got,

 

in that link they have given in verilog code we have to use  synthesis attributes in this way i.e., ----> //synthesis attribute ram_style = block

but it is not working.

 

I have gone through xilinx design constrints guide there they have mentioned some thing like this ----> (*ram_style = "block" *)  , i have tested this on chip , it is working . (It should be used in verilog code itself).

 

If i have not used properly former attribute please let me know.

 

Still pending issue is "inferring ram style from XPS GUI" (Though in verilog attributes can be used , i want to know like project navigator GUI , XPS GUI does have this feature ??)

 

Thanks in advance,

Regards,

Krishna Kishore 

 

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