UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor mehmettukel
Visitor
11,934 Views
Registered: ‎08-29-2013

Bug: Xilinx ISE 14.4 (if - generate) structure

Hi Xilinx guys,

I discovered a possible BUG in your tool. I think it is a serious one. Please, look at the following VHDL code.

I have two if-generate structures depending on the value of NEIGHBOR constant which is defined in a package. The synthesizer is supposed to create first if generate when NEIGHBOR is 0 (zero). But it tries to check size mismatch regardless of if-generate structures and found a (-1) index in signal inputFifo(NEIGHBOR - 1). So it gives an error and stops. I think your synthesizer first evaluates the signal size mismatch in all the file, to catch possible errors to improve error catching time/compile time. However the error XST gives is against the VHDL standart. I also synthesized my code under Cadence RTL Compiler to prove my argument. Cadence RC succesfully reads and elaborates the design. If you want to do a test case with my code, you can just select NETWORK_WIDTH as 4.

Please reply me ASAP.

Thanks,

Mehmet

 

 

 

--following two if-generate structures provide inputFifoNeighborChanger
withoutNeighbor: if NEIGHBOR = 0 generate
begin
	widthCounterLimitIn <= NETWORK_WIDTH - 1;
	fifoExtInMux <= fifoExtIn;
end generate withoutNeighbor;
	
withNeighbor: if NEIGHBOR > 0 generate
begin
	widthCounterLimitIn <= (NETWORK_WIDTH - 1 + 2 * NEIGHBOR) when neighborSelIn = '1' else
				(NETWORK_WIDTH - 1) when neighborSelIn = '0';
	fifoExtInMux <= inputFifo(NEIGHBOR - 1) when neighborSelIn = '1' else
	fifoExtIn when neighborSelIn = '0';
end generate withNeighbor;
----------------------------------------------------------------------

 

 

0 Kudos
13 Replies
Xilinx Employee
Xilinx Employee
11,904 Views
Registered: ‎10-24-2013

Re: Bug: Xilinx ISE 14.4 (if - generate) structure

Hi,
Can you please attach the archived project that demonstrates the issue you are seeing?
Thanks,Vijay
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
0 Kudos
Visitor mehmettukel
Visitor
11,875 Views
Registered: ‎08-29-2013

Re: Bug: Xilinx ISE 14.4 (if - generate) structure

Hi Vijay,

I am attaching here a test case for this issue; and I got the same error for this test code too.

Regards,

Mehmet

0 Kudos
Moderator
Moderator
11,869 Views
Registered: ‎07-21-2014

Re: Bug: Xilinx ISE 14.4 (if - generate) structure

Hi,

 

1. Use new parser to synthesize the code. Set "-use_new_parser yes" in synthesis property to get proper error message.

2. You are trying to update input direction signal.

 

Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
Search for documents/answer records related to your device and tool before posting query on forums.
Search related forums and make sure your query is not repeated.

Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
Helpful answer -> Give Kudos
-----------------------------------------------------------------------------------------------

 

Thanks
Anusheel
0 Kudos
Visitor mehmettukel
Visitor
11,855 Views
Registered: ‎08-29-2013

Re: Bug: Xilinx ISE 14.4 (if - generate) structure

Hi,
I got the same error with that option "-use_new_parser yes". So, what are you saying? Is it not against the standart?
Mehmet
0 Kudos
Moderator
Moderator
11,850 Views
Registered: ‎07-21-2014

Re: Bug: Xilinx ISE 14.4 (if - generate) structure

Hi,

 

I am getting below error:

ERROR:HDLCompiler:294 - "C:\..\exp.vhd" Line 34: Cannot update 'in' object cikis
ERROR:HDLCompiler:294 - "C:\..\exp.vhd" Line 38: Cannot update 'in' object cikis
ERROR:HDLCompiler:854 - "C:\..\exp.vhd" Line 30: Unit <behavioral> ignored due to previous errors.

 

Can you post your error message here?

 

Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
Search for documents/answer records related to your device and tool before posting query on forums.
Search related forums and make sure your query is not repeated.

Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
Helpful answer -> Give Kudos
-----------------------------------------------------------------------------------------------

Thanks
Anusheel
0 Kudos
Visitor mehmettukel
Visitor
11,845 Views
Registered: ‎08-29-2013

Re: Bug: Xilinx ISE 14.4 (if - generate) structure

With default parser.

---------------------

Entity <exp> compiled.
ERROR:HDLParsers:3367 - "/home/homeless/projects/tez/ifgenerate/exp.vhd" Line 34. -4 is not included in the index range, 10 downto 0, of array giris.
ERROR:HDLParsers:1402 - "/home/homeless/projects/tez/ifgenerate/exp.vhd" Line 34. Object cikis of mode IN can not be updated.
ERROR:HDLParsers:1402 - "/home/homeless/projects/tez/ifgenerate/exp.vhd" Line 38. Object cikis of mode IN can not be updated.

 

With new parser.

------------------

Parsing entity <exp>.
Parsing architecture <Behavioral> of entity <exp>.
ERROR:HDLCompiler:294 - "/home/homeless/projects/tez/ifgenerate/exp.vhd" Line 34: Cannot update 'in' object cikis
ERROR:HDLCompiler:294 - "/home/homeless/projects/tez/ifgenerate/exp.vhd" Line 38: Cannot update 'in' object cikis
ERROR:HDLCompiler:854 - "/home/homeless/projects/tez/ifgenerate/exp.vhd" Line 30: Unit <behavioral> ignored due to previous errors.
VHDL file /home/homeless/projects/tez/ifgenerate/exp.vhd ignored due to errors

0 Kudos
Moderator
Moderator
11,838 Views
Registered: ‎07-21-2014

Re: Bug: Xilinx ISE 14.4 (if - generate) structure

Hi,

 

You are declaring "cikis : in  STD_LOGIC" and you are assigning a value to it "cikis <= giris(0);".

That's the reason XST showing the error.

Make cikis as out to resolve the issue.

 

Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
Search for documents/answer records related to your device and tool before posting query on forums.
Search related forums and make sure your query is not repeated.

Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
Helpful answer -> Give Kudos
-----------------------------------------------------------------------------------------------

Thanks
Anusheel
0 Kudos
Visitor mehmettukel
Visitor
11,811 Views
Registered: ‎08-29-2013

Re: Bug: Xilinx ISE 14.4 (if - generate) structure

Hi Anusheel,

That was not the problem in my real project actually. Apparently, I forgot to change the type of the port when I created a test project for you.

When I corrected the type of the port, with default parser it still gives the same error. But with passing an extra argument "-use_new_parser yes", it does not give the error. So can you verify that default parser of XST does not parse the file according to VHDL standart. Because if that is the case, I want to know. Actually you have to declare it somewhere. Cannot handling if-generate structure seems very serious to me. I have lots of them in my project. By the way, why are you keeping your default parser as it is. Besides, I haven't seen a property in ISE gui under synthesis options, I am simply passing the argument after you told me so. Where is it actuallyin the GUI?

Thanks.

Mehmet

0 Kudos
Moderator
Moderator
11,803 Views
Registered: ‎07-21-2014

Re: Bug: Xilinx ISE 14.4 (if - generate) structure

Hi,

 

We recommend to use "-use_new_parser yes" new parser for older devices.

Default parser is best suited for new devices.

 

GUI flow:

Go to synthesis -> process properties -> Synthesis Options -> Other XST Command Line Options -> type -use_new_parser yes

 

Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
Search for documents/answer records related to your device and tool before posting query on forums.
Search related forums and make sure your query is not repeated.

Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
Helpful answer -> Give Kudos
-----------------------------------------------------------------------------------------------

 

 

Thanks
Anusheel
0 Kudos
Visitor mehmettukel
Visitor
9,291 Views
Registered: ‎08-29-2013

Re: Bug: Xilinx ISE 14.4 (if - generate) structure

How on earth VHDL syntax is related with the device? I am asking whether the default parser correctly parses the VHDL code or not? I am talking about if-generate structure here... Does your default parser correctly parse IF-GENERATE structure of VHDL or not? Simple Yes or No question...

Please...

Mehmet


@anusheel wrote:

Hi,

 

We recommend to use "-use_new_parser yes" new parser for older devices.

Default parser is best suited for new devices.

 

GUI flow:

Go to synthesis -> process properties -> Synthesis Options -> Other XST Command Line Options -> type -use_new_parser yes

 

Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
Search for documents/answer records related to your device and tool before posting query on forums.
Search related forums and make sure your query is not repeated.

Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
Helpful answer -> Give Kudos
-----------------------------------------------------------------------------------------------

 

 


 

0 Kudos
Moderator
Moderator
9,280 Views
Registered: ‎07-21-2014

Re: Bug: Xilinx ISE 14.4 (if - generate) structure

Hi,

 

For new devices starting from 6 series, default parser is set to new_parser and for old devices, default parser is set to old_parser.

Issues with the old_parser are fixed in the new_parser.

We have seen few similar issues with old_parser that's the reason I suggested you to use new parser.

 

Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
Search for documents/answer records related to your device and tool before posting query on forums.
Search related forums and make sure your query is not repeated.

Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
Helpful answer -> Give Kudos
-----------------------------------------------------------------------------------------------

 

Thanks
Anusheel
0 Kudos
Historian
Historian
9,260 Views
Registered: ‎02-25-2008

Re: Bug: Xilinx ISE 14.4 (if - generate) structure


@mehmettukel wrote:

How on earth VHDL syntax is related with the device? I am asking whether the default parser correctly parses the VHDL code or not? I am talking about if-generate structure here... Does your default parser correctly parse IF-GENERATE structure of VHDL or not? Simple Yes or No question...


What he means is that "newer" families (which I think means S6 and V6) by default use this "new" parser when synthesizing, and "older" families use the old parser.

 

The "old" parser had issues with language support, mainly because as the language evolved (from VHDL-93 to VHDL-2002 and later) it did not support new features. The "new parser" adds some new features (which I would list but I can't remember the link to where they're listed) and should be used all the time in spite of the dire warnings that the tool spits out when you use it.

 

So that is basically how VHDL syntax is related to the device. Ridiculous, yes.

 

But to answer your question: I have not seen either parser not handle if-generates incorrectly, and I use them (as well as for-generates) extensively. That doesn't mean there is not a case where it blows up. 

----------------------------Yes, I do this for a living.
0 Kudos
Visitor mehmettukel
Visitor
9,242 Views
Registered: ‎08-29-2013

Re: Bug: Xilinx ISE 14.4 (if - generate) structure

Hi bassman59,

I understood what he said. Thanks anyway.

Changing the type of parser according to device does not make sense to me. Besides it is not explicitly declared in the properties of XST. You need to guess the name of the argument that you pass to XST.

 

If I write a code according to VHDL-93 standart, I expect the same behaviour for all devices. Isn't the standarts are created for this purpose? Yes, I am aware of the extensions that are brought to if-generate structure in VHDL-200x. So I have intentionally used the syntax that is valid for both VHDL93 and 200x.

 

The thing that bothers me is, XST changes the parser according to device but keeps both of them. If the new parser fixes the issues that older one has (as stated by anusheel) , why not just XST uses new parser by default. Instead they change it not according to standart (it would have made a lot of sense, if they had done that) but according to device. My doubt is the new one is not mature yet.

P.S: There is another different behaviour between two parsers regarding the usages of constants that are declared in a package. One of them gives error the other one does not. I found a way around it.

Be safe everyone.

Regards,

Mehmet

0 Kudos