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Observer id314159
Observer
981 Views
Registered: ‎03-14-2018

Bug found? Alias, unconstrained range, no warning when out of range

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Dear Xilinx community,

 

I just had to deal with a very annoying problem which cost me a lot of time to figure out and I think this might actually be a bug (and not just "(not) covered by the specification"):

(I'm working with Vivado 2017.4, implementation was for the Kintex-7 kc705 evaluation platform with the xc7k325tffg900-2 on it.)

 

I have an out signal "sig_out", let's say a standard_logic_vector(7 downto 0).

I specify aliases, some only std_logic, some std_logic_vector. For simplicity, let's say I only have the following two:

alias alias1: std_logic is sig_out(0);

alias alias2: std_logic_vector is sig_out(7 downto 1);

At some point I want to write data to them. (Why else would I have them defined to that out port...)

So in the meantime I understood that my alias2 does have the range 7 downto 1, which is fine. (One could also think that it might have 6 downto 0, but that's not the matter.)

 

The problem now occurs when I nevertheless do something like the following:

alias1 <= some_bit;

alias2(6 downto 0) <= some_bits;

 

While apparently the elaboration for the simulation is smart enough to check the ranges and see that alias2 has 7 downto 1 and not 6 downto 0 and reports this, this does not seem to hold for the implementation. Instead, in the implementation, Vivado seems to think "ah, alias2 is simply an alias to sig_out, sig_out has the range 7 downto 0, so let's simply take this as "sig_out(6 downto 0)"". Obviously, this is bad, since now my sig_out(0) will have two drivers.

 

I assume this is an error in the implementation, which should check for valid ranges even for aliases just as the simulation elaboration does? If so, I hope someone in charge might notice this and this might be fixed in the future. (If not already fixed in the 18.1 version, but I simply assume such an atypical problem is simply not known.)

 

It drove me nuts to find this...

 

Best regards

1 Solution

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Xilinx Employee
Xilinx Employee
1,319 Views
Registered: ‎02-16-2014

Re: Bug found? Alias, unconstrained range, no warning when out of range

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Hi @id314159

 

Able to reproduce this issue at my end and Filed a CR to fix this issue.

5 Replies
Scholar richardhead
Scholar
941 Views
Registered: ‎08-01-2012

Re: Bug found? Alias, unconstrained range, no warning when out of range

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Can you post the real code. I am using aliases quite extensively and have no issues.

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Xilinx Employee
Xilinx Employee
1,320 Views
Registered: ‎02-16-2014

Re: Bug found? Alias, unconstrained range, no warning when out of range

Jump to solution

Hi @id314159

 

Able to reproduce this issue at my end and Filed a CR to fix this issue.

Observer id314159
Observer
896 Views
Registered: ‎03-14-2018

Re: Bug found? Alias, unconstrained range, no warning when out of range

Jump to solution

I also just found out by accident that it doesn't even check if the length of the range matches when you specify the alias range.

I.e. the following is implemented somehow:

 

alias alias1: std_logic_vector(4 downto 0) is some_bits(10 downto 1);

Just to make sure this is also known and hopefully fixed.

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Scholar jmcclusk
Scholar
889 Views
Registered: ‎02-24-2014

Re: Bug found? Alias, unconstrained range, no warning when out of range

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This is why I gave up using aliases over 10 years ago..    weird stuff happens constantly.

Don't forget to close a thread when possible by accepting a post as a solution.
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Xilinx Employee
Xilinx Employee
854 Views
Registered: ‎02-16-2014

Re: Bug found? Alias, unconstrained range, no warning when out of range

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Hi @id314159

 

Yes, I see same issue and filed CR to provide error for range mismatches in alias.

 

Thanks,

Manusha

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