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CODING/Synthesis Question

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Participant
Posts: 48
Registered: ‎11-22-2016
Accepted Solution

CODING/Synthesis Question

Hello All,

In the example designs I often come across a concept where a constant named DLY is declared and assigned as say 1 ns.

 

They have used the same constant in the code as follows:

 

process(USER_CLK)
begin
if   (USER_CLK'event and USER_CLK = '1') then
     channel_up_cnt <= (others => '0') after DLY;
elsif(CHANNEL_UP = '1') then
   if(channel_up_cnt = X"1F") then
        channel_up_cnt <= channel_up_cnt after DLY;
   else
         channel_up_cnt <= channel_up_cnt + 1 after DLY;

  end if;
end process;

 

My Question:

Does this DLY synthesis during synthesis process?...If yes, how does this DLY thing gets inferred?

 

Thank you,

Manoj


Accepted Solutions
Highlighted
Teacher
Posts: 4,667
Registered: ‎03-31-2012

Re: CODING/Synthesis Question

@manoj_xilinx this DLY is for simulation purposes only (to introduce something like clock to output delay which is normally not visible in simulation) and it is completely ignored for synthesis.

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All Replies
Moderator
Posts: 1,352
Registered: ‎01-16-2013

Re: CODING/Synthesis Question

@manoj_xilinx,

 

Delay is ignored by Vivado synthesis.

 

--Syed

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Highlighted
Teacher
Posts: 4,667
Registered: ‎03-31-2012

Re: CODING/Synthesis Question

@manoj_xilinx this DLY is for simulation purposes only (to introduce something like clock to output delay which is normally not visible in simulation) and it is completely ignored for synthesis.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.