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Registered: ‎10-15-2018

Can I use "dont touch" to stop ports and logic from being optimized out.

Hi,

I have a project, to be implemented in Zynq platform, in which some huge frame buffers with many address and data I/O need to be outside of the logic and hence the related huge number of pins are I/O of my module top level.

With so many I/O implementation fails due to too many I/O ports at top level and not enough pins on the FPGA.

I plan to make a wrapper for my top level in which i plan to keep the ports related to the memory buffer as wires and not as I/O. I will be forced to keep them danging as I cannot instantiate a memory and connect it (Then it will try to synthesize that huge memory and fail consequently). I am trying to do this still, but will this strategy see the dangling ports and optimize out the connected logic in my IP/RTL since it is connected to ports that are dangling. If yes, what is the best way to handle this ? Should I just apply dont touch to the logic and module instances that are connected to these ports ?

 

Also, I think this might be a common problem faced when using huge memory buffers that communicate with I/O. Keeping the buffers internal leads to BRAM over utilization, keeping them outside leads to too many address and data I/O added and hence I/O over utilization. What is the recommended practice ?

Thanks a lot in advance and sincerely

Bhawandeep Singh

 

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Moderator
Moderator
86 Views
Registered: ‎07-21-2014

Re: Can I use "dont touch" to stop ports and logic from being optimized out.

@bhawandeepsingh

If this is a top module then OOC mode cannot be used. 

You can create a wrapper and mark other ports(in submodules) and logic as DONT_TOUCH, but please verify the design functionality as many ports and nets are not used tool may still optimize some logic. 

Thanks
Anusheel 

Thanks
Anusheel
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