11-06-2013 05:29 PM
e.g: connect an inout signal from Pin1 to Pin2 inside FPGA without any logic
11-06-2013 05:45 PM
What do you mean by an inout? An inout is a Verilog construct that indicates stuff about the ability to drive into or out of a module.
There is no direct equivalent to this in hardware. The closest thing we have is an IOBUF, which is an output driver that can be tristated and an input buffer. If the output buffer is enabled (by enabling the EN pin of the IOBUF), the value on the O pin of the IOBUF drives onto the IO pin. If the output is disabled, then an external driver can drive a value onto (effectively) the IO pin of the IOBUF, and the input can drive the value from the IO pin to the I pin.
But, this is different than the concept of a Verilog inout, which doesn't have an enable signal - it is as if the wire inside the module and the wire outside the module are the same wire.
Given this, there is no equivalent to "tying two pins of the FPGA together" as if they were the same wire.
11-06-2013 11:34 PM
Do you mean a verilog inout signal cann't be connected from Pin to Pin inside FPGA/CPLD?
So,one side must be uni-direction,and other can be inout.
11-07-2013 12:23 AM
avrumw's explanations are correct.
You can not convert FPGA IOs into simple bidirectional wires.
See the datasheet to understand what an IOB is made of.
The inout port constructs of HDLs like verilog and VHDL are intended for various things.
Simulations, Tri-State port modelling and simplifying internal feedback (Wher VHDL also offers the buffer type).
You shouldn't use inout ports for internal function blocks, and for I/O pins only if you do the tristate handling inside your design.
e.g. say you have a port 'bi_dir' in your design, then inside your design you need something like:
if output_enable = '1' then
bi_dir <= data_out;
bi_dir <= 'Z';
data_in <= bi_dir; -- the input path is always active
From this code you can see that when the design drives data to the output it also sees these values on the data_in.
At the other times it sees the data coming from the outside.
This also implies that there must not be driving conflicts between inside and outside drivers.
Now if you would connect the input and output drivers of two IOBs crosswise without using the TRISTATE feature, what would happen?
The active output drivers would act against some possible input, causing an output shortening in the worst case.
The signal level on the input then might become indeterminable and the whole loop will hang in some strange state.
It might even cause severe damage to the drivers.
What you can do is using a direction signal to choose the driving direction using the tristate drivers alternating.
This would result in something like the well known 74xx245 bidirectional line driver.
Have a nice synthesis