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999068709169

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11-13-2020 05:46 AM

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Registered:
09-08-2009

Can someone explain me, almost double LUT resources utilization with less bits

Using 12=> utilization is 6 LUTS

Using 11=> utilization is 11 LUTS

```
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_test is
port(
dataout : out std_logic := '0';
en : in std_logic;
clk : in std_logic
);
end pwm_test;
architecture rtl of pwm_test is
constant NUM_OF_CLK80MHZ_COUNTS_FOR_20US : positive := 1599;
constant CNTR_NUM_BITS : positive := 11;
signal pwm_cntr_max : unsigned(CNTR_NUM_BITS - 1 downto 0) := to_unsigned(NUM_OF_CLK80MHZ_COUNTS_FOR_20US, CNTR_NUM_BITS);
signal pwm_cntr : unsigned(pwm_cntr_max'range) := (others => '0');
begin
process_pwm_cntr : process(clk)
begin
if rising_edge(clk) then
if ((pwm_cntr = pwm_cntr_max) or en = '0') then
pwm_cntr <= (others => '0');
else
pwm_cntr <= pwm_cntr + 1;
end if;
end if;
end process;
-- output becomes high when counter reaches half max.
process_dataout : process(clk)
begin
if rising_edge(clk) then
if (en = '1') then
if (pwm_cntr <= pwm_cntr_max(CNTR_NUM_BITS - 1 downto 1)) then
dataout <= '0';
else
dataout <= '1';
end if;
else
dataout <= '0';
end if;
end if;
end process;
end architecture rtl;
```

Vivado 2018.3

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999068709169

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11-13-2020 05:52 AM

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Registered:
09-08-2009

In the real design with multiple files the difference is 6LUTs vs 13LUTs

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drjohnsmith

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11-13-2020 05:53 AM

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Registered:
07-09-2009

you have a less than or equal

pwm_cntr <= pwm_cntr_max(CNTR_NUM_BITS - 1 downto 1)

look at how that function is made in logic.

if you want to check a counter has reached half way in hardware,

its different to software.

If you have a 12 bit counter,for the first half of the count the top bit is '0', for theother half of the count , the top bit is '1'.

so all you need to do is compare the top bit ,

if you want to compare two numbers to see if one is bigger than the other,

then its less logic to subtract one from the other, and check the carry bit,

If you look at even the smaller subtract method,

the propagation time through the subtractor can be "long" and its normal to add a register to the subtraction and the data , called pipe lining,

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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999068709169

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11-13-2020 07:24 AM

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Registered:
09-08-2009

@drjohnsmith thanks for your reply.

I am not checking if a counter has reached halfway, I am checking if the counter has reached its halfway __of max value__

Even if I was , whether the counter is 11 or 12 bits , I should be comparing only top bit.

pwm_cntr_max is constant ,0b110 0011 1111 so I am comparing a 11 or 12 bits counter with 0x63F and 0x31F.

My fear and real point is, I should not be adding 1 more unused bit (1599 can be represented by 11 bits) doing completely the same functionality resulting in a smaller circuit.

Whether it is doing subtraction or any other algorithm, this should be the job of the logic optimizer.

I should not be saying "Perhaps I should try 16 bits pwm_counter_max and pwm_counter , maybe it will end up 4 LUTs."

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drjohnsmith

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11-13-2020 09:10 AM

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Registered:
07-09-2009

A few things,

you are not coding a compare as you say, but a greater or equal to .

try drawing out the logic you would do to make a greater than equal to , and see how it explodes as the number of bits increases.

BTW have you simulated to check it works as you intend, its easy for logic to be removed without you realising till you simulate.

Do you have timing constraints in place ?

remember the tools are a deep and murky thing...

their aim is to make a design that fits in your device and meets your timing constraints.

i.e. they run till that is meet and stop

They do not optimise to make the smallest code , nor the fastest,

So without any of the above, yes the tools could well make one representation double the size of the other,

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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