11-13-2020 05:46 AM
Using 12=> utilization is 6 LUTS
Using 11=> utilization is 11 LUTS
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity pwm_test is port( dataout : out std_logic := '0'; en : in std_logic; clk : in std_logic ); end pwm_test; architecture rtl of pwm_test is constant NUM_OF_CLK80MHZ_COUNTS_FOR_20US : positive := 1599; constant CNTR_NUM_BITS : positive := 11; signal pwm_cntr_max : unsigned(CNTR_NUM_BITS - 1 downto 0) := to_unsigned(NUM_OF_CLK80MHZ_COUNTS_FOR_20US, CNTR_NUM_BITS); signal pwm_cntr : unsigned(pwm_cntr_max'range) := (others => '0'); begin process_pwm_cntr : process(clk) begin if rising_edge(clk) then if ((pwm_cntr = pwm_cntr_max) or en = '0') then pwm_cntr <= (others => '0'); else pwm_cntr <= pwm_cntr + 1; end if; end if; end process; -- output becomes high when counter reaches half max. process_dataout : process(clk) begin if rising_edge(clk) then if (en = '1') then if (pwm_cntr <= pwm_cntr_max(CNTR_NUM_BITS - 1 downto 1)) then dataout <= '0'; else dataout <= '1'; end if; else dataout <= '0'; end if; end if; end process; end architecture rtl;
11-13-2020 05:53 AM
11-13-2020 07:24 AM
@drjohnsmith thanks for your reply.
I am not checking if a counter has reached halfway, I am checking if the counter has reached its halfway of max value
Even if I was , whether the counter is 11 or 12 bits , I should be comparing only top bit.
pwm_cntr_max is constant ,0b110 0011 1111 so I am comparing a 11 or 12 bits counter with 0x63F and 0x31F.
My fear and real point is, I should not be adding 1 more unused bit (1599 can be represented by 11 bits) doing completely the same functionality resulting in a smaller circuit.
Whether it is doing subtraction or any other algorithm, this should be the job of the logic optimizer.
I should not be saying "Perhaps I should try 16 bits pwm_counter_max and pwm_counter , maybe it will end up 4 LUTs."
11-13-2020 09:10 AM