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xchen2000
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8,990 Views
Registered: ‎11-18-2009

Can't even get a simple up-counter working today :(

I am using Xilinx 7.1, kind of old, but it worked fine until today

 

Today, I need to create a very simple up-counter in my xc9572xl.


If I use 2-bit counters, it works fine:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

 

entity xxx is
    port (
        mclk: in std_logic; -- this is the same as adclk              
        cnt_latch: buffer std_logic_vector  (1 downto 0)
    );
end xxx;

...
signal counter: std_logic_vector  (1 downto 0);

 

cnt_latch(1 downto 0) <=   counter (1 downto 0);

 

count_up: process (mclk) begin
 if (rising_edge (mclk)) then
  counter <=   counter+1;
 end if;
end process count_up;

When I increase the size of counter to 8, :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

 

 

entity xxx is
    port (
        mclk: in std_logic; -- this is the same as adclk              
        cnt_latch: buffer std_logic_vector  (1 downto 0)
    );
end xxx;

 

...

 


cnt_latch(7 downto 0) <=   counter (7 downto 0);

signal counter: std_logic_vector  (7 downto 0);
count_up: process (mclk) begin
 if (rising_edge (mclk)) then
  counter <=   counter+1;
 end if;
end process count_up;

 

The result: the lowest 2 bits still work, but the upper 6 bits are a big mess

101010101010101010  --- works fine

001100110011001100  --- works fine

101101001011010010  --- wrong, should be 0000111100001111

101101010100101010  --- wrong, should be 0000000011111111

.....

 

 

Any pointers?

 

 

Thanks!

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29 Replies
xchen2000
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Registered: ‎11-18-2009

The second declaration was a typo when I posted the question (not in the real test), but the problem stays

    

cnt_latch: buffer std_logic_vector  (1 downto 0)

 

should be

 

cnt_latch: buffer std_logic_vector  (7 downto 0)

 

 

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bassman59
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Registered: ‎02-25-2008

don't use std_logic_arith!

 

Use numeric_std.

 

Make your counter type an integer or natural instead of a std_logic_vector.

 

Your life will be easier.

----------------------------Yes, I do this for a living.
barriet
Xilinx Employee
Xilinx Employee
8,971 Views
Registered: ‎08-13-2007

Agreed.

 

Other thoughts:

-have you properly constrainted the clock? Does the design meet timing? Are you targeting the correct speed grade part?

-do you have the I/O pins assigned properly?

 

Those are frequent causes of similar issues. I've seen others such as

-voltages out of spec

-SI problems on the clock. Is it free running from an oscillator or are you trying to pulse this with some test fixture, switch, etc.

-not correctly measuring the signals you are interested in (wrong pins, wrong equipment or methodology, etc.)

 

bt

barriet
Xilinx Employee
Xilinx Employee
8,969 Views
Registered: ‎08-13-2007

I just remembered another possible cause - it wasn't my first thought since so much time has passed:

http://www.xilinx.com/support/answers/21168.htm (7.1i CPLD Hprep6 XC9500/XL/XV CoolRunner XPLA3 - Device (Jedec) output does not function properly on the board)

I've seen this before on a design (also 95XL) that just didn't work as expected despite a lot of initial head scratching. Updating the software to 7.1.04i and rebuilding the design fixed the issue.

http://www.xilinx.com/support/answers/10959.htm (ISE Install - Where can I find and download old service packs for ISE?)

http://www.xilinx.com/support/download/index.htm (Downloads)

 

bt

xchen2000
Visitor
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8,967 Views
Registered: ‎11-18-2009

Thx, but the same problem:

 

The result: the lowest 2 bits still work, but the upper 6 bits are a big mess

101010101010101010  --- works fine

001100110011001100  --- works fine

101101001011010010  --- wrong, should be 0000111100001111

101101010100101010  --- wrong, should be 0000000011111111

 

 

>>>>

 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity XXX is
    port (
        mclk: in std_logic; -- this is the same as adclk              
        cnt_latch: buffer std_logic_vector  (7 downto 0)
    );
end XXX;

architecture Behavioral of XXX is
signal counter: integer;
signal endcounter: integer;
signal adclkcounter: std_logic_vector  (1 downto 0);


begin

cnt_latch(7 downto 0) <=  CONV_STD_LOGIC_VECTOR( counter, 8 );

count_up: process (mclk) begin
    if (rising_edge (mclk)) then
            counter <=   counter+1;
    end if;
end process count_up;


end Behavioral;
 

 

 

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xchen2000
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Registered: ‎11-18-2009

The clock is only 4Mhz

 

I am sure the I/O pins work fine. If I break down the 8 bit counters into several 2 bit countes, it works, but that approach seems stupi

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xchen2000
Visitor
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8,962 Views
Registered: ‎11-18-2009

Futher question if we got this integer working

 

My final requirement is a 28 or 32 bit counter and output them through a 8 bit pins

 

I assume interger is 32-bit? if not, what do I use? can I specify the size of an integer variable?

 

How do I output certain portion of an insteger to IO pins? CONV_STD_LOGIC_VECTOR( counter, 8 ) seems handle the lowest 8 bits only

 

Thank you all for your time!

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drjohnsmith
Teacher
Teacher
8,961 Views
Registered: ‎07-09-2009

Hi

 

you still have arith in there, get rid of it.

 

you have IO type of buffer, not how I'd do things,  inputs or outputs:

 

 

 have a look here for a nice simple counter example

 

http://www.asic-world.com/vhdl/first1.html

 

I seem to remeber there is one in the editor templates of ISE as well.  

   just paste it in.

 

BTW:  How do you know what the outputs are ? Are you simulating or in real hardware

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
xchen2000
Visitor
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Registered: ‎11-18-2009

I read the output from hardware directly

 

If I remove std_logic, how do I output integer to IO port?

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bassman59
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8,766 Views
Registered: ‎02-25-2008


xchen2000 wrote:

I read the output from hardware directly

 

If I remove std_logic, how do I output integer to IO port?


RTFM for numeric_std.

 

You want 

 

outsig_slv <= std_logic_vector(to_unsigned(count_integer, 'outsig_slv));

 

and that's the way to do it.

----------------------------Yes, I do this for a living.
xchen2000
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Registered: ‎11-18-2009

Also, in your example,

 

http://www.asic-world.com/vhdl/first1.html

 

It uses "

signal pre_count: std_logic_vector(3 downto 0);

 

 

It is against this suggestion "Make your counter type an integer or natural instead of a std_logic_vector."

 

Don't know whom I should listen to now ....

 

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bassman59
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Registered: ‎02-25-2008


xchen2000 wrote:

Futher question if we got this integer working

 

My final requirement is a 28 or 32 bit counter and output them through a 8 bit pins

 

I assume interger is 32-bit? if not, what do I use? can I specify the size of an integer variable?


Please, go out and buy a good VHDL textbook -- these questions are all answered there.

 

Declare your integer as a range:

 

    signal mycount : integer range 0 to (2**28) -1;

 

will give you an unsigned integer that's 28 bits wide.

 

To output over an 8-bit bus you'll have to do a byte-select. There's a few examples of how to do this out there on the web.

----------------------------Yes, I do this for a living.
bassman59
Historian
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Registered: ‎02-25-2008


xchen2000 wrote:
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity XXX is
    port (
        mclk: in std_logic; -- this is the same as adclk              
        cnt_latch: buffer std_logic_vector  (7 downto 0)
    );
end XXX;

architecture Behavioral of XXX is
signal counter: integer;
signal endcounter: integer;
signal adclkcounter: std_logic_vector  (1 downto 0);


begin

cnt_latch(7 downto 0) <=  CONV_STD_LOGIC_VECTOR( counter, 8 );

count_up: process (mclk) begin
    if (rising_edge (mclk)) then
            counter <=   counter+1;
    end if;
end process count_up;


end Behavioral;
 

 

 


You're mixing numeric_std and std_logic_arith -- do NOT do that. Get rid of CONV_STD_LOGIC_VECTOR.

----------------------------Yes, I do this for a living.
xchen2000
Visitor
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Registered: ‎11-18-2009

I appreciate your time, and if you can suggest a good VHDL book, I thank you.  At this point, I do have a book, obviously, it is not god enough

 

Anyway, change it again, still no good

 

>>>>>>>

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity XXX is
    port (
        mclk: in std_logic; -- this is the same as adclk              
        cnt_latch: buffer std_logic_vector  (7 downto 0)
    );
end XXX;

architecture Behavioral of XXX is
signal counter: integer;


begin

cnt_latch(7 downto 0) <=  std_logic_vector(to_unsigned(counter, 8));


count_up: process (mclk) begin
    if (rising_edge (mclk)) then
            counter <=   counter+1;
    end if;
end process count_up;


end Behavioral;

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bassman59
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Registered: ‎02-25-2008


xchen2000 wrote:

I appreciate your time, and if you can suggest a good VHDL book, I thank you.  At this point, I do have a book, obviously, it is not god enough

 

Anyway, change it again, still no good

 

>>>>>>>

 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity XXX is
    port (
        mclk: in std_logic; -- this is the same as adclk              
        cnt_latch: buffer std_logic_vector  (7 downto 0)
    );
end XXX;

architecture Behavioral of XXX is
signal counter: integer;


begin

cnt_latch(7 downto 0) <=  std_logic_vector(to_unsigned(counter, 8));


count_up: process (mclk) begin
    if (rising_edge (mclk)) then
            counter <=   counter+1;
    end if;
end process count_up;


end Behavioral;


Why are you using buffer ports?

 

Declare cnt_latch as out std_logic_vector(7 downto 0); and you should be good to go.

As for a good VHDL book, the current edition of Peter Ashenden's is considered to be pretty good.
----------------------------Yes, I do this for a living.
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8,743 Views
Registered: ‎07-15-2008

Yikes I’ve never do the stuff that is being suggested toyou. I certainly wouldn’t use an integer.

I don’t really think there is that much wrong with yourdescription, in fact I think it’s pretty good.

 

Here is how I’d do it, if this doesn’t work either there isa hardware problem or Xilinx have got something wrong.

 

 

Just out of interest, do examine the RTL schematic producedby this description, then change it to 2 bit and re-examine the produced rtlschematic. What do you make of that?

 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

 

 

entity COUNT_UP is

    Port ( mclk : instd_logic;

           cnt_latch :out std_logic_vector(7 downto 0));

end COUNT_UP;

 

architecture Behavioral of COUNT_UP is

 

 

signal counter_sig : std_logic_vector (7 downto 0);

 

begin

 

 

process (mclk)

begin

 

if (mclk 'event and mclk = '1') then

 

                                counter_sig<= counter_sig +1;

 

                                elsenull;

                                endif;

end process;

 

  cnt_latch <=     counter_sig;

 

end Behavioral;

 

 

 

 

Oh btw, all the noise made about the arith library isbecause its vendor defined not ieee controlled. Having arith and unsigned atthe same time probably leads to clashes too. 

 

So why are these both declared by default in the template ofthe Xilinx tool your using? Well I don’t know….

 

Have a good day Bobster 

8,740 Views
Registered: ‎07-15-2008

Just FYI, I had a quick look, and  here is a coding example from the xilinx xstuser guide 2009 (the Xilinx standard)

This has a reset (which to be honest I’d always include too)

 

Note the lack of any Integer values

 

--

--4-bit unsigned up counter with an asynchronous reset.

--

libraryieee;

useieee.std_logic_1164.all;

useieee.std_logic_unsigned.all;

 

entitycounters_1 is

 

port(C,CLR : in std_logic;

Q :out std_logic_vector(3 downto 0));

endcounters_1;

 

architecturearchi of counters_1 is

 

signaltmp: std_logic_vector(3 downto 0);

 

begin

process(C, CLR)

begin

if(CLR=’1’) then

tmp<= "0000";

elsif(C’event and C=’1’) then

tmp<= tmp + 1;

endif;

endprocess;

Q<= tmp;

end archi;

 

 

Kind Regards Bobster 

xchen2000
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Registered: ‎11-18-2009

bobster_the_lobster, thank you

 

Taking  bassman5's pointer, I did go back to ReadThe**bleep**ingManual.

 

As you said, his accusation of std_logic_vector, even the buffer vs output, is baseless, It is more a personal preference than correct path :)

 

I just moved my project from ISE 7.1 to Webpack 11, and as you said, my codes were perfectly fine, it is a Xilinx's bug!

 

 

 

 

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drjohnsmith
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Registered: ‎07-09-2009

Hi

 

I am NOT gfoing to get into a flame war here,

 

comments:

 

If you ask a general Home work type question on the forum, of how could I do something, you are going to get lots of different answers.

 

Personal preferance you say. Well most people I work for have programing style manuals.Especialy the bigger companies.

 

       all say don't use buffers on IO's

       all say only use std_logic(vector) for io of modules

       all say dont' use proprietry packages like std_logic_arith

       all say use integers for things like counters as they simulate faster than the multi level std_logic_vector.

 

Ok, it's personal preferance, but there is a lot of experiance on this forum, you do your way it could be the new thing, but for now I'd still recomend the outline above.

 

 Good luck with your new style,

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
barriet
Xilinx Employee
Xilinx Employee
8,729 Views
Registered: ‎08-13-2007

I suspect the jedec bug I mentioned was the cause of the code not working if you were originally using 7.1.

 

Yes, there are many ideas on coding styles. But as John said, there are many common trends as a result of experiences with much larger projects. These tend to get distilled into coding guidelines to help avoid such repeating common issues. Personally I do not generally use records, especially in sythesizable code. I do know people who use them extensively, including as I/O in modules. Do these people tend to have issues that don't show up otherwise? Sometimes they do. Can it work? Apparently. Would I recommend it? No.

 

Many of the comments here are likely well intentioned to help you develop good practices that may likely appreciate later as you progress from this foundation. They may not be the direct cause of a particular issue, but are likely the best time for the people to give this constructive feedback.

 

bt

 

 

xchen2000
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Registered: ‎11-18-2009

drjohnsmith, thank you!

 

I understand your point and also appreciate your time helping me on this subject

 

When I started to learn to use Xilinx, most examples regarding up counters, from Xilinx or Web, uses std_logic, so that's how I started

 

 

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xchen2000
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timpe, thank you!

 

Many of the comments here are likely well intentioned to help you develop good practices that may likely appreciate later as you progress from this foundation. They may not be the direct cause of a particular issue, but are likely the best time for the people to give this constructive feedback.

 

When I was told to RTFM, I will, but I don't think that was very  "well intentioned"
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barriet
Xilinx Employee
Xilinx Employee
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Registered: ‎08-13-2007

For the record, I did say "many" not "all". - this is a long thread already.. ;)

 

 

 

 

 

xchen2000
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Registered: ‎11-18-2009

bassman59, thank you for your book suggestion
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xchen2000
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timpe, sorry, but I was trying to thank everyone who gave me suggestion, I didn't know Xilinix' server has such a small capacity :D
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bassman59
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bobster_the_lobster wrote:

Yikes I’ve never do the stuff that is being suggested toyou. I certainly wouldn’t use an integer.



Why not? Integers (and naturals) are a perfectly good way of expressing numbers, and in many cases they make life easier for the engineer.

 

You don't HAVE to use them -- but really, they work. 

 

You can also use the numeric_std types signed and unsigned if you prefer.

 


Oh btw, all the noise made about the arith library isbecause its vendor defined not ieee controlled. Having arith and unsigned atthe same time probably leads to clashes too. 

 

So why are these both declared by default in the template ofthe Xilinx tool your using? Well I don’t know….

 

Have a good day Bobster 


Using std_logic_arith is a big fail, especially if you need to mix signed and unsigned numbers in the same entity. Why? Because all of the usual functions and operators (addition, subtraction, etc) are overloaded and the tools will get VERY confused.

 

I have filed repeated Web Cases and enhancement requests, asking Xilinx to stop the including-by-default of the std_logic_arith library use clauses. Xilinx needs to get on the stick. All of the professional recommendations are to use numeric_std.

----------------------------Yes, I do this for a living.
bassman59
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Registered: ‎02-25-2008


xchen2000 wrote: Taking  bassman5's pointer, I did go back to ReadThe**bleep**ingManual.

 

As you said, his accusation of std_logic_vector, even the buffer vs output, is baseless, It is more a personal preference than correct path :)

 


The buffer type is deprecated in the latest version of the language and is likely to be gone soon enough. Which is a good-enough reason not to use them.

 

----------------------------Yes, I do this for a living.
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xchen2000
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Registered: ‎11-18-2009

First, thank you for taking time to answer.

 

I don't question your conclusion "The buffer type is deprecated in the latest version of the language and is likely to be gone soon enough. Which is a good-enough reason not to use them.", since only time can tell, but your statement "Declare cnt_latch as out std_logic_vector(7 downto 0); and you should be good to go."was wrong. Same can be said about your comment about integer.

 

The whole problem is a faulty lib from Xilinx

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xchen2000
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Registered: ‎11-18-2009

Just for the record, "Same for your comment about integer", I was commenting about your suggetion of changing it to integer will fix the problem, not to argure if integer was better or not, it may welll be.
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