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Observer
Observer
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Registered: ‎02-05-2019

Checking Edge of Signal without a process

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Hi,

How is it to use the following statement instead of a clock triggered process .


x <= '1' when y = '1' else '0' when (rising_edge(CLK));

 

does it have any drawback ? or any benefit over process implementation.What are the trade offs.


Thanks and Best Regards,
Muhammad Hamza Muneer

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Scholar
Scholar
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Registered: ‎08-01-2012

Re: Checking Edge of Signal without a process

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@hamzamuneer 

That is a register with async set connected to Y and D conected to '0'

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Registered: ‎06-21-2017

Re: Checking Edge of Signal without a process

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I doubt that could be synthesized.  What would you expect the hardware to look like, based on this code?

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Scholar
Scholar
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Registered: ‎08-01-2012

Re: Checking Edge of Signal without a process

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Current example is useless, as you're asking for '1' for the infinitely small time of the rising edge of the clock and '0' the rest of the time. I think you mean a register like this.

q <= d when rising_edge(clk); 

This infers a process that looks like this

Process(clk)
Begin
  If rising_edge(clk) then
    Q<= d;
  End if;
End process;

Which is a normal process for a sync register. It should be perfectly sunthesisable. What you cannot do is infer a sync reset,  but and async reset is possible.

 

Q <= '0' when reset else d when rising_edge(clk);
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Teacher
Teacher
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Registered: ‎07-09-2009

Re: Checking Edge of Signal without a process

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@richardhead, Was this format only for 2008 ?
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Scholar
Scholar
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Re: Checking Edge of Signal without a process

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@drjohnsmith 

Nope, this style has existed since '87 afaik (using clk'event and clk = '1' as rising_edge was a '93 addition). Whether tools have supported it is another question, but Im pretty sure it has worked for quite some time for some (if not all) tools.

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Observer
Observer
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Registered: ‎02-05-2019

Re: Checking Edge of Signal without a process

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Thank you for your reply, this is synthesizeable and is working fine on vivado 2018.3. I just wanted to know how the synthesizer understands it 

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Observer
Observer
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Registered: ‎02-05-2019

Re: Checking Edge of Signal without a process

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No This works for all versions
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Observer
Observer
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Registered: ‎02-05-2019

Re: Checking Edge of Signal without a process

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Hello,
Thank you for reply,

I have changed the original question as the original example was not very clear,

x <= '1' when y = '1' else '0' when (rising_edge(CLK));


Can you please tell how the above line of code will be synthesized, I have tried synthesizing it, it works fine and the functionality is as expected, but i am unsure how synthesizer takes this
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Scholar
Scholar
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Registered: ‎08-01-2012

Re: Checking Edge of Signal without a process

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@hamzamuneer 

That is a register with async set connected to Y and D conected to '0'

View solution in original post

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Observer
Observer
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Registered: ‎02-05-2019

Re: Checking Edge of Signal without a process

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Thank you
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Teacher
Teacher
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Registered: ‎07-09-2009

Re: Checking Edge of Signal without a process

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@richardhead
I can hardly remember time before rising_edge !

What I was wondering,
this is such a short hand way of writing a register,

Whats the disadvantage of

q <= d when rising_edge( clk );

over writing

process( clk )
begin
if rising_edge( clk ) then
Q <= D;
end if;
end process;
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Scholar
Scholar
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Re: Checking Edge of Signal without a process

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@drjohnsmith 

The process form allows more flexability, as you could include syncronous resets and enables. In the shorthand, you could write:

q <= d when (rising_edge(clk) and en = '1');

But you may be open to some clock gating (Though I think in FPGAs the tools are clever enough not to).

With 2008, you can use aggregates on the LHS, so you can be even more concise:

(op0, op1, op2, op3) <= (ip0, ip1, ip2, ip3) when rising_edge(clk);

 I think this is mostly a quesiton of style. What used to always work sticks, and people generally dont change (and text books never get updated or replaced)

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: Checking Edge of Signal without a process

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Im wondering about resources,
especially in the simulator,

Im sort of thinking, with the process / sensitivity list, the simulator is scheduling for the next clock, on all other deltas , it ignores the process,
where as the system without a sensitivity list, will have to be evaluated on every delta.

For one or two registers, no difference, but I'm wondering with many tens of thousands of registers if it would make a difference .



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Scholar
Scholar
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Registered: ‎08-01-2012

Re: Checking Edge of Signal without a process

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@drjohnsmith 

A inline assignment is only sensitive to the signals on the RHS of the assignment, so my previous exmaple would have a sensitivity list of clk, ip1, ip2, ip3, ip4.

Simulators are very optimised now, so sensitivity lists are pretty imaterial. remember VHDL2008 added process(all) so a process is sensitive (technically) to all signals available. In reality the compiler will just work out what its senstive to from the contents during compilation.

A process without a sensitivity list must have a wait statement in it, otherwise its an illegal process.

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: Checking Edge of Signal without a process

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Thank you @richardhead

As for vhdl 2008, and process(all)
that as far as I understand was only added because of pressure from Verilog people.
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Scholar
Scholar
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Registered: ‎08-01-2012

Re: Checking Edge of Signal without a process

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@drjohnsmiththat and the fact that adding all the required signals to an async process is tedious and error prone.  Verilog has had always @* for a very long time,  and it hasn't slowed their stimulation down. 

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: Checking Edge of Signal without a process

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@richardhead

thank you, I'll call this , thank you

Your comment,

"adding all the required signals to an async process is tedious and error prone"
sort of misses the basic point of vhdl,
its equivalent to the double entry book keeping, or when data is typed, you do it more than once, to find typing errors,
The point of VHDL, is to find all these silly errors before synthesis / simulation , chip layout.

You say
" it hasn't slowed their (Verilog) stimulation down"

thats is a totalyy illogical statement, how can you quantify that statement,

Thank you for the chat though, and apologies to the original poster for taking over the post,
it has been very informative and thought provoking

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Scholar
Scholar
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Registered: ‎08-01-2012

Re: Checking Edge of Signal without a process

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@drjohnsmith 

But sensitivity lists are nothing to do with VHDL typing and nothing like double entry book-keeping. They are a user instruction to the compiler that "this process should only be evaluated when these signals change". Its all too easy and possible to leave a signal out and cause a simulation synthesis missmatch because you forgot one, and its not always obvious whats missing. Even more dangerous, it is possible in some cases that different logic can be formed from a traditionally bad sensitivity list.

eg.  Quartus will synth this as a register:

 

process(clk)
begin
  if clk = '1' then
    q <= d;
  end if;
end process;

 

 

whereas this becomes a latch:

process(clk, d)
begin
  if clk = '1' then
    q <= d;
  end if;
end process;

The only difference here is the sensitivity lists. Quartus is technically correct making a reg with this, as q is only updated when clk changes to a '1' from something else. But this flies against accepted norms of VHDL templates.

Back to the process(all), here, you're telling the compiler to do the work for you. Its not taking anything away from VHDL linting strengths, because it was never a check on anything. Only an instruction. Verilog has had always @(*) for 20+ years, and its use is highly encouraged.

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: Checking Edge of Signal without a process

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Can I suggest you try it
You will see that this error will be flagged in VHDL,
as it should be

I really do think @richardhead that we are done here,
if you want to carry this on, send us a PM,

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Scholar
Scholar
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Re: Checking Edge of Signal without a process

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@drjohnsmith 

There is no such thing as an "incorrect" sensitivity list. Synthesis tools will give warnings (and only a warning) that a sensitivity list is incomplete because it interprets processes in a different way and ignores the lists (and generates it's own list from the contents of the process). A simulator will NEVER give a warning or an error for an incomplete sensitivity list, as missing signals are not an error. The simulator has no way of knowing what's "missing" or not.

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