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891 Views
Registered: ‎03-21-2018

Common [17-233] Vivado 16.2 Synthesizing block design failed

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[Common 17-223] Fail to read message file E:/vivado fyp files/SOC Design ADS/SOC2/SOC2.runs/synth_1/.Xil/Vivado-8956-LochanaPC/realtime/tmp/26E40067B80.rtd.pb. Please check permission of the directory and existence of the file.

 

Please help me to fix this error.

I checked the specified folder .Xil and it does not contain any files.

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Moderator
Moderator
1,117 Views
Registered: ‎02-07-2008

Hi @lochanamendis, try without any spaces in the project path and/or Xilinx installation path.

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Moderator
Moderator
1,118 Views
Registered: ‎02-07-2008

Hi @lochanamendis, try without any spaces in the project path and/or Xilinx installation path.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

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874 Views
Registered: ‎03-21-2018

Thanks @peadard for solving my problem as soon as the problem raised.

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