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Explorer
Explorer
5,175 Views
Registered: ‎09-27-2013

Compile VHDL package? 2016.3

The Vivado can't find my custom package/custom types, even though I have included the file in Design Sources/Simulation Sources, and it is enabled, type: VHDL, Library: xil_defaultlib.

 

In the package file, I have the standard stuff:

 

package std_logic_array_vector_pkg is

In the code I'm trying to call it from:

 

library xil_defaultlib;
use xil_defaultlib.std_logic_array_vector_pkg.all;

Hovering over the squiggly red line, I get: "Error: Cannot find <std_logic_array_vector_pkg> in library <xil_defaultlib>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file."

 

This project was upgraded from an earlier Vivado version, if that matters. The simulator still seems to work fine, but this "error" squiggly line is peppered all throughout my code.

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Xilinx Employee
Xilinx Employee
5,157 Views
Registered: ‎02-16-2014

Re: Compile VHDL package? 2016.3

Hi @rdb9879

 

Can you try using as below?

use work.std_logic_array_vector_pkg.all;

 

Please see Morgan's post in below thread where similar issue is discussed.

https://forums.xilinx.com/t5/7-Series-FPGAs/A-VHDL-package-in-Vivado/td-p/660301

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Explorer
Explorer
5,149 Views
Registered: ‎09-27-2013

Re: Compile VHDL package? 2016.3

That seems to work (pun intended), but I don't understand why this works.

 

In my Sources/Libraries tab, everything is listed under "xil_defaultlib", and there is no mention of a library named "work."

 

 

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