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Visitor
Visitor
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Registered: ‎09-10-2013

Conflict on KEEP property (Warning:Xst:638)

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Hi,

 

I am writing a VHDL design in which I have to keep and recognize after synthesis all my signals declared in VHDL files by their initial names. So I used the keep attribute like that :

 

signal temp                   : std_ulogic_vector(31 downto 0);
signal temp_after_r     : std_ulogic_vector(31 downto 0);

 

attribute keep : string;

attribute keep of temp                      : signal is "true";  
attribute keep of temp_after_r        : signal is "true";

 

This attribute is efficient for most of the signal declared in my design but for several buses, that generates a warning on the 32 bits of the bus :

WARNING:Xst:638 - in unit shift Conflict on KEEP property on signal temp(23) and temp_after_r(31) temp_after_r(31) signal will be lost.

Naturally, the bus temp_after_r doesn't exist anymore in the synthesis netlist.

 

In the design, the signals engaged in the warning are implemented like that :

  temp_after_r(31 downto 24) <= temp(23 downto 16);
  temp_after_r(23 downto 16) <= temp(15 downto  8);
  temp_after_r(15 downto  8) <= temp(7  downto  0);
  temp_after_r( 7 downto  0) <= temp(31 downto 24);

 

It's important that I keep both of these signals in the synthesis netlist, so do you know where the problem could come from ? If it comes from my implementation ?

 

Thank you very much !

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Historian
Historian
10,711 Views
Registered: ‎02-25-2008

@moreaub wrote:

Ok, thank you very much !

 

So do you know if there is a kind of artifice for keeping both signals without altering the behavior of the design ? 

 


You keep missing the point.

 

They are the SAME SIGNAL. So the tools retain only one name. Any mechanism for "keeping both signals" necessarily alters the behavior of the design.

----------------------------Yes, I do this for a living.

View solution in original post

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Historian
Historian
8,229 Views
Registered: ‎02-25-2008

@moreaub wrote:

Hi,

 

I am writing a VHDL design in which I have to keep and recognize after synthesis all my signals declared in VHDL files by their initial names. So I used the keep attribute like that :

 

signal temp                   : std_ulogic_vector(31 downto 0);
signal temp_after_r     : std_ulogic_vector(31 downto 0);

 

attribute keep : string;

attribute keep of temp                      : signal is "true";  
attribute keep of temp_after_r        : signal is "true";

 

This attribute is efficient for most of the signal declared in my design but for several buses, that generates a warning on the 32 bits of the bus :

WARNING:Xst:638 - in unit shift Conflict on KEEP property on signal temp(23) and temp_after_r(31) temp_after_r(31) signal will be lost.

Naturally, the bus temp_after_r doesn't exist anymore in the synthesis netlist.

 

In the design, the signals engaged in the warning are implemented like that :

  temp_after_r(31 downto 24) <= temp(23 downto 16);
  temp_after_r(23 downto 16) <= temp(15 downto  8);
  temp_after_r(15 downto  8) <= temp(7  downto  0);
  temp_after_r( 7 downto  0) <= temp(31 downto 24);

 

It's important that I keep both of these signals in the synthesis netlist, so do you know where the problem could come from ? If it comes from my implementation ?

 

Thank you very much !


Those four assignments mean that the signals on the right hand side and the left hand side are identical. 

How would you propose that they be kept separate?

----------------------------Yes, I do this for a living.
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Xilinx Employee
Xilinx Employee
8,217 Views
Registered: ‎05-14-2008

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Visitor
Visitor
8,204 Views
Registered: ‎09-10-2013

Ok, thank you very much !

 

So do you know if there is a kind of artifice for keeping both signals without altering the behavior of the design ? For example, introducing a logic gate in order to "break" the net. I have already tried to insert a AND gate with only '1'  on an input like that :

 

  temp_after_r(31 downto 24) <= temp(23 downto 16) and x"FF";
  temp_after_r(23 downto 16) <= temp(15 downto  8) and x"FF";
  temp_after_r(15 downto  8) <= temp(7  downto  0) and x"FF";
  temp_after_r( 7 downto  0) <= temp(31 downto 24) and x"FF";

 

But implemented like that, after synthesis, AND gate is reduced as a wire and the signal is still lost.

 

Even if the design is not optimized, my challenge is to find all signals before and after synthesis.

So if you have an idea, thanks !

 

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Historian
Historian
10,712 Views
Registered: ‎02-25-2008

@moreaub wrote:

Ok, thank you very much !

 

So do you know if there is a kind of artifice for keeping both signals without altering the behavior of the design ? 

 


You keep missing the point.

 

They are the SAME SIGNAL. So the tools retain only one name. Any mechanism for "keeping both signals" necessarily alters the behavior of the design.

----------------------------Yes, I do this for a living.

View solution in original post

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Highlighted
Visitor
Visitor
8,176 Views
Registered: ‎09-10-2013

Ok, thank you very much Bassman59 !

 

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