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374 Views
Registered: ‎11-24-2020

Connect and synthesize multiple top-modules

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Hi! I hope you are well.

I am trying to synthesize a processor on Artix-7 FPGA using Vivado 2020.1. Basically, I have 8 main Design Sources (top-modules), of which three of them have submodules. Besides, all of them share the same constraints file.

I need to connect the inputs/outputs of the modules between them to have a bigger and complete processor. However, I can only synthesize each top-module separated and cannot generate all the required pins at once. Hence, can someone help me or redirect me to some material/tutorial on how to synthesize all the top-modules at once to link the modules? Instead, generate some script with all the connections and generate a synthesis for all modules at once?

I am new to Vivado, and I did not find yet something that can help me.

 

Thank you.

TopModules.png
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Scholar
Scholar
323 Views
Registered: ‎08-01-2012

Hi

This is usually where you could create another HDL module that instantiates all the other modules and connects them how you need. then use this new file as your top level.

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Scholar
Scholar
324 Views
Registered: ‎08-01-2012

Hi

This is usually where you could create another HDL module that instantiates all the other modules and connects them how you need. then use this new file as your top level.

View solution in original post

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314 Views
Registered: ‎11-24-2020

Great idea. To make sure I followed up:

Should I create a block design, insert all the modules, and manually connect all of them? Afterward, I make this block design the top module?

 

Thanks for your help.

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Scholar
Scholar
291 Views
Registered: ‎08-01-2012

Either that, or write some HDL to do it yourself (likely verilog as thats what all the other files are). Using block design locks you into Vivado.

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279 Views
Registered: ‎11-24-2020

I will try to do it. Thank you very much for your help.

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