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Could not resolve non-primitive black box cell 'cmpy_v6_0_12_viv'

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Observer
Posts: 36
Registered: ‎09-09-2016
Accepted Solution

Could not resolve non-primitive black box cell 'cmpy_v6_0_12_viv'

I am attempting to use both Complex Multiplier (cmpy_v6_0_12) and DDS Compiler (dds_compiler_v6_0_13) IP in Vivado 2017.1. I am able to create the IP using the the GUI wizard and then synthesize the design. I want to generate an EDIF netlist with a stub file, and a DCP so that I have the option later to either use the EDIF or the DCP (I know the DCP contains an EDIF). Later, I attempt to use the EDIF netlist (or DCP file) in a non-project/ooc design and run synthesis and implementation.

I have tried the following:
1:
Create IP from Catalog using GUI
Synthesize in OOC mode
write_checkpoint
open checkpoint in GUI
write_edif
write_vhdl -mode port ...


2:
Create IP from Catalog using GUI
Synthesize in global mode
Open Synthesized design
write_checkpoint
write_edif

write_vhdl -mode port ...

Then, in another design where the IP module is instantiated in VHDL, I read_edif and read the VHDL stubfile (or just read_checkpoint), and then I run synthesis and write the edif/dcp again.

Synthesis succeeds with the following warning:
CRITICAL WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'cmpy_v6_0_12_viv' instantiated as 'rv/worker/inst_ComplexMult/U0/i_synth' [......./cmpy_0.edf:132]

I get this same warning if I create a post-synthesis project and "Open Synthesized Design" with the only source-file being the EDIF file from IP's synthesis.

When I open up the netlist or checkpoint after this synthesis, I see one of the sub-modules of each IP as a Black Box. In the case of Complex Multiplier, I have the following hierarchy in the netlist:
".../myInst_ComplexMult/U0/i_synth". Here, "U0" is an instance of "cmpy_v6_0_12", and "i_synth" is an instance of "cmpy_v6_0_12_viv" and is a BLACK BOX.

This black box ultimately leads to the following error during opt_design:
ERROR: [DRC INBB-3] Black Box Instances: Cell '......./worker/inst_ComplexMult/U0/i_synth' of type '......../worker/inst_ComplexMult/U0/i_synth/cmpy_v6_0_12_viv' has undefined contents and is considered a black box.  The contents of this cell must be defined for opt_design to complete successfully.

I run into a nearly identical situation with DDS Compiler.

I have researched this error for ~16 hours and encountered many threads/answers, but none of them have helped me to resolve this. I welcome any responses (even ones referencing threads I may already have visited). To replicate the synthesis warning I just create the cmpy or dds_compiler IP, synthesize it, write_edif, create a post-synth project containing only that edif, and open the synthesized design. To recreate the error, I instantiate the IP in a vhdl design, read in the vhdl stub and edif (or just dcp), and run synthesis and implementation.


Accepted Solutions
Moderator
Posts: 5,391
Registered: ‎09-20-2012

Re: Could not resolve non-primitive black box cell 'cmpy_v6_0_12_viv'

Hi @dbanks12

 

As these are encrypted IP's, Vivado's "write_edif" command actually produces multiple files.

One is a plain text wrapper file, the other will contain encrypted EDIF for areas protected by security attributes. Please ensure you are reading in both of these EDIF files.

 
Thanks,
Deepika.
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Moderator
Posts: 1,298
Registered: ‎07-21-2014

Re: Could not resolve non-primitive black box cell 'cmpy_v6_0_12_viv'

@dbanks12

 

This issue occurs when opened synthesized design does not load IP checkpoints. Use "Open Synthesized Design" and see whether these checkpoints were loaded or not.

 

After using write_checkpoint on fully loaded design, the flow should work.

 

Thanks,
Anusheel
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Moderator
Posts: 5,391
Registered: ‎09-20-2012

Re: Could not resolve non-primitive black box cell 'cmpy_v6_0_12_viv'

Hi @dbanks12

 

As these are encrypted IP's, Vivado's "write_edif" command actually produces multiple files.

One is a plain text wrapper file, the other will contain encrypted EDIF for areas protected by security attributes. Please ensure you are reading in both of these EDIF files.

 
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
Observer
Posts: 36
Registered: ‎09-09-2016

Re: Could not resolve non-primitive black box cell 'cmpy_v6_0_12_viv'

Thank you @vemulad and @anusheel. When including EDIF files, I now include both the edif generated as well as the EDN file that is generated as a side effect. I also had to make sure there was no "syn_black_box" or other lines in the stub file indicating a black box. I am not sure why it was not working with the DCP files though....

 

I am now running into a different but related issue. I am attempting to simulate and run the implemented design. No matter what inputs I give the two modules (cmpy and dds_compiler), their outputs always remain undefined. The demo testbenches work after generating the IP, but when I use the IP cores in my own design in non-project/ooc mode, their outputs are always undefined. I tried mimicking the testbench's functionality in my non-project design, but the outputs remained undefined no matter what.

 

For simulation, I am including the VHDL file underneath "Simulation" for each IP. So, I am including dds_compiler_0.vhd and cmpy_0.vhd. Is there something I am missing?

Observer
Posts: 36
Registered: ‎09-09-2016

Re: Could not resolve non-primitive black box cell 'cmpy_v6_0_12_viv'

I will close this since my original question was answered. I have opened up a new thread with my new question: https://forums.xilinx.com/t5/Simulation-and-Verification/Simulated-IP-modules-have-undefined-outputs/td-p/773211