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Newbie
Newbie
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Registered: ‎10-01-2009

DCM synthesis direct with DRP feature

Hello,

my environment.
1. Virtex4 XC4VLX200
2. Synplifypro 8.8
3. ISE 10.2 sp3
4. CoreGen 10.1.03(nt64), Single DCM_ADV 9.1i

I want to use DCM Dynamic Reconfiguration Ports (DRP) to
reconfigure PHASE_SHIFT parameter.
I design a controler to send DWE, DEN, ADDAR ... signal,
the RTL simulation is pass.

I used XST + ISE10.1 sp3,
the post P&R simulation is pass, too.

but either I used Synplify pro 8.8 or 8.9,
after ISE P&R,
the post P&R simulation is fail, phase is never changed.
it seems Synplifypro needs other synthesis direct or constraints.

 

I have tested some methods on website,
but no one can work.
http://www.xilinx.com/support/answers/11074.htm
http://www.xilinx.com/support/answers/11095.htm

Attached file is the DCM that I generated by CoreGen,

I didn't add any synthesis direct, constraint or parameter in sdc, ncf, ucf.

 
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