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Visitor
Visitor
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Registered: ‎01-04-2017

[DRC UTLZ-1] Resource utilization: OLOGIC over-utilized in Top Level Design (Vivado 2020.1)

Hi!

I have project for Artix-7, almost all input-output ports are used. It works fine in Vivado 2018.3. But after upgrade to Vivado 2020.1 it returns error:
[DRC UTLZ-1] Resource utilization: OLOGIC over-utilized in Top Level Design (This design requires more OLOGIC cells than are available in the target device. This design requires 336 of such cell types but only 285 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)

Synthesis Report Utilization shows than the project uses 336 OLOGIC, but only 285 OLOGIC are available. It is strange because only 168 output ports is used.

Vivado 2018.3 does not check OLOGIC at Synthesis stage, only at Implementation stage.


There is a small example in attachment. It creates one 3-state io-port. And all three buffers for this port (input and output data registers (reg_i and reg_o) and enable register (reg_en)) are selected to be placed to IOB.

Synthesis Report Utilization for this small examples shows that 2 (TWO) OLOGIC is used: OUTFF_register uses 1 OLOGIC, and TFF_register uses 1 OLOGIC. But it is wrong! OUTFF_register and TFF_register use the same OLOGIC! Not two different ones. And schematic confirms it: both registers are put to the same OLOGIC.

Implementation Report Utilization for this small examples shows correct result: only 1 (ONE) OLOGIC is used.

Please, correct Vivado 2020.1!

And while patch is not ready, is it possible to disable OLOGIC check?

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6 Replies
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269 Views
Registered: ‎01-22-2015

@yuklimov 

Instead of inferring IOBUF, does instantiating it per UG953 give you are workaround?

entity top is
    port(
        clk_i : in STD_LOGIC;
        data_i : in STD_LOGIC;
        data_en : in STD_LOGIC;
        data_o : out STD_LOGIC;
        data_io : inout STD_LOGIC
        );		
end top;

architecture top of top is  
    signal data_i_reg, data_en_reg, data_o_reg : std_logic;
    signal reg_o1, reg_o2, reg_i, reg_en : std_logic;
    attribute iob : string;
    attribute iob of reg_o2, reg_i, reg_en : signal is "true";
    
begin
    IOBUF_inst : IOBUF
    generic map (
        DRIVE => 12,
        IOSTANDARD => "DEFAULT",
        SLEW => "SLOW")
    port map (
        O => reg_o1,    -- Buffer output
        IO => data_io,  -- Buffer inout port (connect to top-level port)
        I => reg_i,     -- Buffer input
        T => reg_en     -- 3-state enable input, high=input, low=output
    );
        
    process(clk_i)
    begin
        if rising_edge(clk_i) then
            data_i_reg <= data_i;
            data_en_reg <= data_en;            
            reg_i  <= data_i_reg;
            reg_en <= data_en_reg;                      
            reg_o2  <= reg_o1;
            data_o_reg <= reg_o2;
        end if;
    end process;
    
    data_o <= data_o_reg;
end top;
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Xilinx Employee
Xilinx Employee
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Registered: ‎05-14-2008

Try this command and see if this can bypass the DRC check:

set_property IS_ENABLED FALSE [get_drc_checks UTLZ-1]

-vivian

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Highlighted
Visitor
Visitor
238 Views
Registered: ‎01-04-2017

No, the result with IOBUF (instead of vhdl code for 3-state io) is totally same.

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Visitor
Visitor
236 Views
Registered: ‎01-04-2017

No. I added this command to xdc-file and ran it in TCL console (before run synthesis and simulation), but the result is the same.

I can't set 0 to this property:

set_property IS_ENABLED FALSE [get_drc_checks UTLZ-1]
get_property IS_ENABLED [get_drc_checks UTLZ-1]
1
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Xilinx Employee
Xilinx Employee
191 Views
Registered: ‎05-14-2008

Can you provide a test case for us to reproduce the issue?

So the Synthesis process failed that you're not able to launch implementation, correct?

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
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Highlighted
Visitor
Visitor
178 Views
Registered: ‎01-04-2017

Hi, Viviany!

In attachment small testing project for 2020.1 for Artix-7 100T (with 285 IO ports). It uses only 254 IO ports.

Synthesis completed, but in its Utilization report 500 OLOGICs are used (but only 285 OLOGICs are available in this Artix-7).

Implementations failed with this error:

  • Implementation
    • Place Design
      • DRC
        • Floorplan
          • Pblock
            • [DRC UTLZ-1] Resource utilization: OLOGIC over-utilized in Top Level Design (This design requires more OLOGIC cells than are available in the target device. This design requires 500 of such cell types but only 285 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)
      • [Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
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