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123xilinx123
Visitor
Visitor
7,389 Views
Registered: ‎11-26-2008

Difference in Coregen 11. 1 and Corgen 10.1.03 in distributed memory reset generation

hello,

 

My intention is to generate a distributed memory with output data registered.

In coregen 10.1.03, when output option is indicated as 'registered' I am able to get the reset options in the next page.

(reset_qpso and synchronous reset qspo)

 

I 've observed that in Coregen 11.1 even when the output is registered, reset options are greyed out.

I am using Virtex 5 device.

Why is there a difference in Coregen 11. 1 and Corgen 10.1.03 in distributed memory reset generation ?

 

 

regards

Siby Thachil

 

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8 Replies
drjohnsmith
Teacher
Teacher
7,380 Views
Registered: ‎07-09-2009

Hi

 

I don't know, and I don't have data sheet to hand easily, and it might be a red hearring,  but does the V5 output register of the ram have a reset ?

 

 

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drjohnsmith
Teacher
Teacher
7,380 Views
Registered: ‎07-09-2009

Hi

 

I don't know, and I don't have data sheet to hand easily, and it might be a red hearring,  but does the V5 output register of the ram have a reset ?

 

 Other thought,are you using the error checking option, I seem to remeber somethign about this, but can't rmember what !

  Again could be a wild goose chase, but a thought.

 

 

 

 

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123xilinx123
Visitor
Visitor
7,369 Views
Registered: ‎11-26-2008

hi,

 

The coregen modules of ditributed ram has  QPSO_SRST port to reset the flop which has the output of the LUT-RAM.

Please refer to the document ISE\coregen\ip\xilinx\primary\com\xilinx\ip\dist_mem_gen_v3_1\doc\dist_mem_gen_ds322.pdf

 

In coregen 11.1 the option of QPSO_SRST is greyed out. Where as I am able to generate the distributed ram with QPSO_SRST port in Coregen 10.1.03.

 

Thanks,

Siby

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drjohnsmith
Teacher
Teacher
7,362 Views
Registered: ‎07-09-2009

Hi

 

just managed to get to a pc to habe a look,

 

I'd say , that you have found a bug.

  I get the same on ISE 11.3 gen 4.2,  for both the V4 and V5.

 

 very strange.

 

Suggest you talk to your FAE and rase a web case on it.

 

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123xilinx123
Visitor
Visitor
7,358 Views
Registered: ‎11-26-2008

thank you.

I have raised a web case.

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balkris
Xilinx Employee
Xilinx Employee
7,353 Views
Registered: ‎08-01-2008

This is known issue for Xilinx You need install patch to solve this issue 

 

Please contact   Xilinx Tech Support for this issue.

 

To obtain technical support for this patch, please go to
   http://www.xilinx.com/support/techsup/tappinfo.htm to create a WebCase.

 

 This issue  fully addressed in DMG v4.3.

Thanks and Regards
Balkrishan
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drjohnsmith
Teacher
Teacher
7,344 Views
Registered: ‎07-09-2009

Hi Balkrishaniitg

 

I did an admittedly quick search of the errata on MIG, 

  is there an errata / known issues I can refer other people too,

 

 

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balkris
Xilinx Employee
Xilinx Employee
7,312 Views
Registered: ‎08-01-2008

 

 

 

Xilinx Provide link in Core generator for release notes/error errata  

Please refer attached snaps

Thanks and Regards
Balkrishan
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MIG.bmp
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