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fpgalearner

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09-25-2020 02:41 PM

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04-11-2016

Division in ultrascale+ devices

Hi,

Is there any way to do better division in ultrascale+ devices?

I have a design running at 125 MHz (8ns Pulse) and I do a large number division (125000000/115200) and it consumes 43 LUTs and 130 CARRY8 and have 34.087ns data path delay and that leading to -26.233ns setup timing violation.

Regards

P.S. I do such division in my design to calculate clocks per bit for UART and is intended to alter on the fly.

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richardhead

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09-26-2020 12:53 AM

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08-01-2012

If the calculation has both numerator and denominator as fixed, why even bother with it at all? does one of these ever change? how are you doing the division? are you using a divide IP core? Or simply a/b in the RTL?

If you can convert it into a A * (1/N) calculation where (1/N) is already calculated in fixed point, it will be much faster and much smaller.

u4223374

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09-26-2020 05:03 AM

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**any** approach to division will be better than the obvious approach (ie the "/" operator). It's easy (and compact) to make a divider that'll give you one bit of output per clock cycle. The absolute maximum that you'll generate is a 27-bit number, so you could have this division completed in under 30 cycles. I suspect that for a UART, a ~30 cycle setup delay would be irrelevant (30 cycles at 125MHz = ~1/36th of a bit at 115200bps).

avrumw

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09-26-2020 12:59 PM - edited 09-26-2020 01:00 PM

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There are relatively few "legal" Baud rates for a UART - there are something like 14 of them. Rather than do the division, why not just have a table of the proper divider for each of the valid UART Baud rates.

Furthermore, most of the Baud rates are related - there is a whole stream of them that are 300*2^N, so if you have the divisor for 300, then you just divide it by 2^N for the other rates. Taking the 300*2^N ones out, that leaves you with something like 6 others (a few of which are related).

A divider seems like overkill here...

Avrum

fpgalearner

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09-27-2020 02:01 PM

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numerator fixed and denominator varying. What do you mean by this? where (1/N) is already calculated in fixed point

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fpgalearner

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09-27-2020 02:02 PM

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@u4223374 can you explain it little bit?

absolute maximum that you'll generate is a 27-bit number

absolute maximum that you'll generate is a 27-bit number

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fpgalearner

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09-27-2020 02:04 PM

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300, 1200, 2400, 4800, 9600, 19200, 38400, 56000, 57600, 115200, 128000, 230400, 460800, 500000, 576000, 921600, 1000000, 1152000, 1500000, 2000000, 2500000, 3000000, 3500000, 4000000,

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richardhead

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09-27-2020 02:22 PM

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08-01-2012

for example.

lets say you had N / 4

Instead of this, you can work out what 1/4 is in fixed point (b0.01) and do a multiplication instead, because a multiply can easily be done in a single clock.

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fpgalearner

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09-28-2020 05:29 AM

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Hi @richardhead @avrumw and @u4223374

In ultrascale+ devices there are dsp blocks. Can I use it for this for efficient divison? If yes, Is there any Xilinx example for this?

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richardhead

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09-28-2020 05:57 AM

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The easiest way is to convert your divide into a multiply, as already suggested.

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fpgalearner

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09-28-2020 07:04 AM

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richardhead

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09-28-2020 08:41 AM

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