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Participant alejandrocristo
Participant
5,666 Views
Registered: ‎07-23-2010

Doubt about Summary generated by XST

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Hello everybody,

 

I have developed a very big circuit with lots of parallel IP cores, and after synthetizing it with XST (ISE), I got the following summary report:

 

smooth3.png

 

As you can see, I have more than 100% in logic utilization. Does that mean that it would be impossible to program the FPGA with my circuit?

 

Thanks in advance!

Alejandro Cristo
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Xilinx Employee
Xilinx Employee
7,140 Views
Registered: ‎01-03-2008

Re: Doubt about Summary generated by XST

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> As you can see, I have more than 100% in logic utilization.

 

Yes for both LUTs and DSP48e resources.

 

> Does that mean that it would be impossible to program the FPGA with my circuit.

 

Yes, it would be impossible.  You need to choose a larger FPGA or create a smaller design.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com

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Xilinx Employee
Xilinx Employee
7,141 Views
Registered: ‎01-03-2008

Re: Doubt about Summary generated by XST

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> As you can see, I have more than 100% in logic utilization.

 

Yes for both LUTs and DSP48e resources.

 

> Does that mean that it would be impossible to program the FPGA with my circuit.

 

Yes, it would be impossible.  You need to choose a larger FPGA or create a smaller design.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com

View solution in original post

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Participant alejandrocristo
Participant
5,646 Views
Registered: ‎07-23-2010

Re: Doubt about Summary generated by XST

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Thank you very much mgett,

 

I am working now in reducing the number of component by making sequential some of the modules.

 

Thanks!

Alejandro Cristo
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Instructor
Instructor
5,634 Views
Registered: ‎08-14-2007

Re: Doubt about Summary generated by XST

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If your design was only off by a small percentage, you might still have a chance of fitting

and it would be worth trying to run translate and map.  The resource usage reported by

the mapper is the final design size and is the most accurate.  Normally it is unreasonable

to expect to use 100% of the device LUTs, especially in very large devices.  Remember that

the LUTs and registers are packed into slices, and it is not always possible to use all

of the slice resources.  So in the end it is the number of "occupied slices", reported by

the mapper, that must be less than or equal to 100%.

 

Other resources like DSP48 or block RAM are usually fixed after synthesis, so you should assume

the design won't fit if any of these is more than 100%.

 

-- Gabor

-- Gabor
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Participant alejandrocristo
Participant
5,631 Views
Registered: ‎07-23-2010

Re: Doubt about Summary generated by XST

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Hi gszakacs,

 

I have tried to map the circuit and this process shows me the following error:

 

ERROR:Pack:2310 - Too many comps of type "DSP48E" found to fit this device.
ERROR:Map:237 - The design is too large to fit the device.  Please check the
   Design Summary section to see which resource requirement for your design
   exceeds the resources available in the device. Note that the number of slices
   reported may not be reflected accurately as their packing might not have been
   completed.

 

So now it is sure that my circuit does not fit in the FPGA. I will work hard to reduce the paralelism as much as possible.

 

Thank you!!

Alejandro Cristo
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Historian
Historian
5,629 Views
Registered: ‎02-25-2008

Re: Doubt about Summary generated by XST

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@alejandrocristo wrote:

Hi gszakacs,

 

I have tried to map the circuit and this process shows me the following error:

 

ERROR:Pack:2310 - Too many comps of type "DSP48E" found to fit this device.
ERROR:Map:237 - The design is too large to fit the device.  Please check the
   Design Summary section to see which resource requirement for your design
   exceeds the resources available in the device. Note that the number of slices
   reported may not be reflected accurately as their packing might not have been
   completed.

 

So now it is sure that my circuit does not fit in the FPGA. I will work hard to reduce the paralelism as much as possible.

 

Thank you!!


Well, since your original design used 554 DSP blocks and the device has only 128, that'll be a lot of work ...

----------------------------Yes, I do this for a living.
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