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[Doubt about synthesis]

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Hello,


I'm pretty new at Vivado and I'm trying to see how much resources (LUT, FF...) will my design use, but it always reports me the same even if I create 64 more instances of one module. One of my source files has a for loop that creates X instances of a module (and it haves submodules) and the number of created instances (X) is defined by a: `define N_INSTANCES 64 in a Verilog header.

 


I don't know if I'm doing something wrong or I'm missing something, I also tried to find the solution on the forum but I didn't see it.


Thanks

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Scholar markcurry
Scholar

Re: [Doubt about synthesis]

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Couple of things - the code you posted is systemverilog.  Make sure Vivado is setup to use the SystemVerilog parser.  (I think renaming your file extension to .sv will cause this to happen automatically, but I may be confusing my tools).

 

Second thing, where is your typedef declared?  The error message seems to be saying you're declaring it at root scope (i.e not within a module or package). You need to move that definition to within (a module, or package).

 

Regards,

 

Mark

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Moderator
Moderator

Re: [Doubt about synthesis]

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@joel.sanchez

 

Check for the netlist  for those 64 instances after opening synthesized design. Also look at the synthesis log and see if there are any warnings or info related to optimization  during synthesis process.

 

Regards

Rohit

Regards
Rohit
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Scholar dpaul24
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Re: [Doubt about synthesis]

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@joel.sanchez,

 

with so so less information it is difficult to provide you a concrete answer.

It depends, how large your base module is, how many times you are instantiating them and the resources used.

Xilinx synth engine also makes design optimization.

 

Please take a look into your synthesis log file located inside your_project.runs\synth_1\

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FPGA enthusiast!
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Scholar u4223374
Scholar

Re: [Doubt about synthesis]

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The obvious cause of this is that only one of the 64 units is connected to an output. In this case, Vivado will recognise that the remaining 63 don't actually do anything and remove them all from the design.

Moderator
Moderator

Re: [Doubt about synthesis]

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@joel.sanchez

 

Start with synthesis log file. I guess tool is removing the logic from the design(need to see log file and RTL to comment on 'why') and you should be able to see the same details in synthesis log.

 

Thanks,

Anusheel 

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Explorer
Explorer

Re: [Doubt about synthesis]

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Hi,

 

first of all thanks, I will look into the log file as soon as I can and will say something with more information. I saw that the log file has around 1000 lines, should I look for something in particular?

 

 

Thanks,

 

Joel

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Explorer
Explorer

Re: [Doubt about synthesis]

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Hi,

 

after looking into log file and make some changes in the code I've been stuck in an error and I can't find any solution on the Internet:

 

Synthesis Command: synth_design -top shire_top -part xc7a200tfbg676-2
[Synth 8-2644] root scope declaration is not allowed in verilog 95/2K mode ["fileA.vh":14]
[Synth 8-2715] syntax error near packed ["fileA.vh":13]
[Common 17-69] Command failed: Vivado Synthesis failed

 

Where the line fourteen is the next typedef:

 

typedef struct packed {
logic a;

logic b;

logic c;
} strA;

 

Can someone help me to debug this error?


@anusheel @u4223374 @dpaul24 @thakurr


Thanks.

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Scholar markcurry
Scholar

Re: [Doubt about synthesis]

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Couple of things - the code you posted is systemverilog.  Make sure Vivado is setup to use the SystemVerilog parser.  (I think renaming your file extension to .sv will cause this to happen automatically, but I may be confusing my tools).

 

Second thing, where is your typedef declared?  The error message seems to be saying you're declaring it at root scope (i.e not within a module or package). You need to move that definition to within (a module, or package).

 

Regards,

 

Mark