02-20-2009 06:47 PM
I am using the Xilinx EDK 10.1 to place and route the OpenSPARC T1 1.6 project onto a Virtex 5 110T FPGA. When doing this, however, the EDK never finishes placement and routing. I let it run for 5 days and it had 6 processes using all the RAM but no CPU usage. I end up canceling the build operation as it should only take a couple of hours at the most. A copy of the log file is attached.
1st of all, is there a way to get more detailed log messages out of the EDK? The log file doesn't offer much granularity.
Second, has anyone else had problems compiling the OpenSPARC T1 in the EDK? I've posted on the OpenSPARC forums and no one has commented, so I don't think anyone's run into these problems.
02-23-2009 10:33 AM - edited 02-23-2009 10:39 AM
I'm using the EDK because that's what's suggested for the OpenSPARC workflow. An EDK project is provided when you download OpenSPARC that has the connections between the crossbar, OpenSPARC, and microblaze all setup so that you just copy in a modified OpenSPARC netlist if you've modified it and place and route.
I have tried importing the project into synplify premier but placing and routing there failed because of the code, which shouldn't have happened. Using EDK is the best option here and it should work. I would still like more granular logging from the EDK which should help debug this if anyone knows how to achieve that.
02-23-2009 03:41 PM