I've got a seemingly simple task, that I've accomplished in the past, which isn't working now. I'm trying to route UART_1 out the EMIO to a couple of package pins. So, I configure the processing system in the block diagram, then make an external port with the resulting UART_1 pin (screenshot below).
My constraints file has the following constraints to set the package pin and iostandard:
Run synthesis, and I get "'set_property' expects at least one object." errors for those pins. Apparently the UART port doesn't exist after synthesis. In fact, the synthesized design schematic shows the UART_1_rxd signal grounded.
I'm not sure why the port is vanishing; I've used EMIO UART before (albeit with Vivado 2016.3, not 2018.1). I've tried everything I can think of: I've changed package pin locations, io standards, deleted and resynthesized, remade the entire project even. This should be a straightforward task, but it's really hanging me up.
Does anyone know why my UART port doesn't show up after synthesis?