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Visitor
Visitor
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Registered: ‎07-03-2018

EMIO UART signals disappear in synthesis

I've got a seemingly simple task, that I've accomplished in the past, which isn't working now. I'm trying to route UART_1 out the EMIO to a couple of package pins. So, I configure the processing system in the block diagram, then make an external port with the resulting UART_1 pin (screenshot below).

Screen Shot 2019-03-07 at 12.23.14 PM.png

My constraints file has the following constraints to set the package pin and iostandard:

set_property PACKAGE_PIN AC16 [get_ports {UART_1_rxd}]
set_property PACKAGE_PIN AE17 [get_ports {UART_1_txd}]
set_property IOSTANDARD LVCMOS33 [get_ports {UART_1_rxd}]
set_property IOSTANDARD LVCMOS33 [get_ports {UART_1_txd}]

Run synthesis, and I get "'set_property' expects at least one object." errors for those pins. Apparently the UART port doesn't exist after synthesis. In fact, the synthesized design schematic shows the UART_1_rxd signal grounded.

Screen Shot 2019-03-07 at 12.28.30 PM.png

I'm not sure why the port is vanishing; I've used EMIO UART before (albeit with Vivado 2016.3, not 2018.1). I've tried everything I can think of: I've changed package pin locations, io standards, deleted and resynthesized, remade the entire project even. This should be a straightforward task, but it's really hanging me up.

Does anyone know why my UART port doesn't show up after synthesis?

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: EMIO UART signals disappear in synthesis

HI @thomas_tolo ,

Did you make sure to update the HDL wrapper for the design (riught click on the BD in the sources window > generate HDL wrapper) or your top level?

I tried with 2018.2 and I had no issue:

 

UART.JPG


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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