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apreis
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Registered: ‎07-12-2021

ERROR: [Synth 8-1717] cannot access memory

Hi all

I get this "ERROR: [Synth 8-1717] cannot access memory"

I am using  2d array not as a memory, my 2d array is a part of  interface (ports of a module)

How can I solve this issue with out changing my inner block interface?

Thanks in advance

Asaf P    

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dpaul24
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Registered: ‎08-07-2014

@apreis ,

Post the part/full RTL code due to which the error occurs.

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markcurry
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Registered: ‎09-16-2009

@apreis Multi-dimensional arrays on ports (and within interfaces) works just fine, and is heavily used within our group.  Multi-dimensional arrays as first class citizens is one of the first, basic, principles within Systemverilog.  So, as @dpaul24 mentions - show us some code, and we should be able to help you out.

Regards,

Mark

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apreis
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Registered: ‎07-12-2021

I can't  up load my files because security issues but I have the file that I am uploading describe the issueץ

not that now I receive the next errors

[Synth 8-2539] port fifo_used must not be declared to be an array ["fifo.v":50]
[Synth 8-2539] port data_out must not be declared to be an array ["fifo.v":47]
[Synth 8-2539] port data_in must not be declared to be an array ["/project/users/apreis/pcie_test/rtl/fifo.v":44]

 

Thanks for all of you for your help

Asaf Preis

 

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markcurry
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Registered: ‎09-16-2009

I think you simply need to rename your files "*.sv" to let Vivado know that the files are SystemVerilog.  There are other ways to get Vivado to do this, but this method is the simplest, IMHO.

Regards,

Mark

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