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krish.iitd
Visitor
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Registered: ‎06-28-2009

ERROR:Xst:2545 - Variable index is not supported in signal.

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Hi all,

 

I am using Xilinx-10.1 design suite and while synthesizing an RTL, XST  tool flags following error:

ERROR:Xst:2545 -"file.v" line 11872: Variable index is not supported insignal. 

 for verilog constructs shown below:

abc_w[{abc_C, 2'h0}+:4] = abc_S; 

 

What is the problem here? ASIC sythesis tools like DC/RC has no issue with such constructs.  Is there any workaround for this problem or is there any other tool that can handle such constructs (for synthesizing to Xilinx FPGA)?

 

Also XST doesn't allow RTL to contain divison operations other than power of 2, so how do we handle divison operations in FPGA?

ERROR:Xst:867 - "file.v" line 474: Operator / is only supported when the second operand is a power of 2. 

for RTL constructs 

div_ln57_w = {su_w[27:1], m_w[32]} / 3'h7; 

 

Please help.

Thanks, 

Krishnaiah 

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gszakacs
Instructor
Instructor
10,493 Views
Registered: ‎08-14-2007

I took a look at this and found:

 

1) "Syntax Check" did not show the error.

2) It seems that the +: syntax is what XST really doesn't like.

 

    for (i = 0;i < 4;i = i + 1)
      abc_w[{abc_C,2'b00}+i] <= abc_S[i];

 

synthesized O.K.

 

Many people use Synplify instead of XST.  There are other third-party synthesis options

as well.

 

As for division, I would generally avoid it, although you can use CoreGen modules to

implement dividers if necessary.  In the case of dividing by a constant, consider

using multiplication instead.

 

Regards,

Gabor

-- Gabor

View solution in original post

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gszakacs
Instructor
Instructor
10,494 Views
Registered: ‎08-14-2007

I took a look at this and found:

 

1) "Syntax Check" did not show the error.

2) It seems that the +: syntax is what XST really doesn't like.

 

    for (i = 0;i < 4;i = i + 1)
      abc_w[{abc_C,2'b00}+i] <= abc_S[i];

 

synthesized O.K.

 

Many people use Synplify instead of XST.  There are other third-party synthesis options

as well.

 

As for division, I would generally avoid it, although you can use CoreGen modules to

implement dividers if necessary.  In the case of dividing by a constant, consider

using multiplication instead.

 

Regards,

Gabor

-- Gabor

View solution in original post

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krish.iitd
Visitor
Visitor
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Registered: ‎06-28-2009

Thanks for a quick response.

 

Since the RTL has so many lines with "+:" operators, I am not sure how to manually change all of them to the way that XST handles. Will Synplify tool be able to handle the constructs with "+:" range specifiers?

 

 

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gszakacs
Instructor
Instructor
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Registered: ‎08-14-2007

Synplify for Lattice has no problem with the +: syntax, so I imagine the full Synplify

would also work fine with this syntax.

 

Regards,

Gabor

-- Gabor
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ywu
Xilinx Employee
Xilinx Employee
8,771 Views
Registered: ‎11-28-2007

XST works fine with the indexed part-select  operator "+:" if it is on the right-hand side (RHS) of the assignment. It also works fine when it is on the left-hand side (LHS) AND the starting index is a constant. Your case uses a variable as the starting index on the LHS and that what XST doesn't like although it's legal.

 

FWIW, your case should work in 11.2 if you're targeting Virtex6 and Spartan6 as XST uses a new Verilog parser for the two new families.

 

Cheers,

Jim

Message Edited by jimwu on 07-07-2009 10:22 AM
Cheers,
Jim
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kwooding
Visitor
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Registered: ‎07-07-2009

Curious (and annoying).

 

Is there any way to force ISE to use the new verilog parser for older families? (e.g. spartan 3A-DSP)? This notation is much more nicely compact

than the alternatives.

 

Also, are these limitations documented anywhere? All I can find in the XST manual is that Variable Part Selects are "supported" (e.g. summary at the end of Ch 8)

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